Composite Field Arithematic Based S-Box For AES Algorithm

This paper presents high throughput iterative and pipelined VLSI architectures of the Advanced encryption standard (AES) algorithm based on composite field arithmetic in polynomial basis. A logical rearrangement has been performed in the byte substitution (S-box) module to reduce the number of gates in the critical path. Also, inversion in GF(24) module has been separately optimized. ASIC implementation of our S-box has comparatively low power and low energy consumption. The iterative and pipelined implementations of AES in field programmable gate array (FPGA) and ASIC using proposed S-box have high hardware efficiency in terms of throughput per unit area (slices in FPGA).

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On the Optimum Constructions of Composite Field for the AES Algorithm

IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing ◽

10.1109/tcsii.2006.882217 ◽

2006 ◽

Vol 53 (10) ◽

pp. 1153-1157 ◽

Cited By ~ 60

Author(s):

X. Zhang ◽

K.K. Parhi

Keyword(s):

Aes Algorithm ◽

Composite Field

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FPGA implementation of compact S-Box for AES algorithm using composite field arithmetic

2015 Annual IEEE India Conference (INDICON) ◽

10.1109/indicon.2015.7443745 ◽

2015 ◽

Cited By ~ 2

Author(s):

Bhoopal Rao Gangadari ◽

Shaik Rafi Ahamed

Keyword(s):

Fpga Implementation ◽

Aes Algorithm ◽

Composite Field

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FPGA Implementation of Protected Compact AES S–Box Using CQCG for Embedded Applications

10.3233/apc210073 ◽

2021 ◽

Author(s):

R. Sornalatha ◽

N. Janakiraman ◽

K. Balamurugan ◽

Arun Kumar Sivaraman ◽

Rajiv Vincent ◽

...

Keyword(s):

Hardware Implementation ◽

Fpga Implementation ◽

Advanced Encryption Standard ◽

Side Channel ◽

Logic Design ◽

Substitution Box ◽

Side Channel Attacks ◽

Aes Algorithm ◽

Composite Field ◽

Embedded Applications

In this work, we obtain an area proficient composite field arithmetic Advanced Encryption Standard (AES) Substitution (S) byte and its inverse logic design. The size of this design is calculated by the number of gates used for hardware implementation. Most of the existing AES Substitution box hardware implementation uses separate Substitution byte and its inverse hardware structures. But we implement the both in the same module and a control signal is used to select the substitution byte for encryption operation and its inverse for the decryption operation. By comparing the gate utilization of the previous AES S–Box implementation, we reduced the gate utilization up to 5% that is we take only 78 EX-OR gates and 36 AND gates for implementing the both Substitution byte and its inverse. While implementing an AES algorithm in circuitry or programming, it is liable to be detected by hackers using any one of the side channel attacks. Data to be added with a random bit sequence to prevent from the above mentioned side channel attacks.

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An Efficient VLSI Design of AES Cryptography in Memory Implementation

International Journal of Recent Technology and Engineering - 2 ◽

10.35940/ijrte.c6188.118419 ◽

2019 ◽

Vol 8 (4) ◽

pp. 1796-1801

Keyword(s):

Low Cost ◽

Vlsi Design ◽

Advanced Encryption Standard ◽

Working Ability ◽

Verilog Hdl ◽

Aes Algorithm ◽

Composite Field ◽

The Cost

This paper depicts a novel sub bytes strategy for executing the executing the advanced encryption standard (AES) algorithm that offers a considerably enhanced cryptographic strength. Our strategy depends on composite field math randomization, which involves a low cost of execution while not adjusting the algorithm, does not decrease the recurrence of the work and maintains an ideal similarity to the distributed standard. In this document, we suggest a fast and knowledgeable execution of AES in memory (AIM) to scramble the whole part of the memory only when needed. We use NVM’s intrinsic logic working ability to implement the AES algorithm instead of adding extra processing parts to the cost-sensitive memory. The proposed design is implemented using Modelsim 6.4 C and Xilinx tool Verilog HDL and simulated. The proposed framework actualized in FPGA Vertex or Spartan-3.The proposed AES system has been made into an IP and effectively connected in encryption application.

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A COMPACT MEMORY-FREE ARCHITECTURE FOR THE AES ALGORITHM USING RESOURCE SHARING METHODS

Journal of Circuits System and Computers ◽

10.1142/s0218126610006633 ◽

2010 ◽

Vol 19 (05) ◽

pp. 1109-1130 ◽

Cited By ~ 19

Author(s):

YONG-SUNG JEON ◽

YOUNG-JIN KIM ◽

DONG-HO LEE

Keyword(s):

Radio Frequency Identification ◽

Resource Sharing ◽

Multiplicative Inverse ◽

Low Area ◽

Aes Algorithm ◽

Composite Field ◽

Encryption And Decryption ◽

Frequency Identification ◽

Encryption Decryption ◽

Operation Frequency

This paper presents a resource-shared 8-bit (RS8) architecture for the AES algorithm, which aims at compacting the hardware architecture and allows hardware resources to be shared efficiently between encryption and decryption without using a memory. The RS8 architecture only requires one combined S-box/S-1-box for encryption, decryption and key expansion. The RS8 architecture implements the multiplicative inverse in the composite field GF((24)2) with resource sharing methods. In addition, the number of XOR gates used by the proposed combined MixColumns/InvMixColumns module is less than half that of the conventional 32-bit architecture. When comparing the RS8 architecture with the conventional 32-bit architecture on a Xilinx Spartan2 FPGA, the number of total equivalent slices is reduced by 51%. Additionally, the highest operation frequency of the RS8 architecture is 66 MHz, and the throughput is 24 Mbps. Therefore, the performance of the RS8 architecture is sufficient for low-area applications such as wireless network devices and radio frequency identification (RFID).

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