Lightweight VLSI Architectures for Image Encryption Applications

Lightweight cryptography offers significant security service in constrained environments such as wireless sensor networks and Internet of Things. The focus of this article is to construct lightweight SPN block cipher architectures with substitution box based on finite fields. The paper also details the FPGA implementation of the lightweight symmetric block cipher algorithm of SPN type with combinational S-box. Restructuring of traditional look-up-table Substitution Box (S-Box) sub-structure with a combinational logic S-box is attempted. Elementary architectures namely the basic round architecture and reduced datawidth architecture incorporating look-up-table and combinational S-Box substructure are compared in terms of area and throughput. Proposed restructure mechanism occupies less FPGA resources with no comprise in the latency and also demonstrates performance efficiency and low power consumption in Xilinx FPGAs. Robustness of the proposed method against various statistical attacks has been analyzed through comparison with other existing encryption mechanisms.

Designing an Efficient and Highly Dynamic Substitution-Box Generator for Block Ciphers Based on Finite Elliptic Curves

Developing a substitution-box (S-box) generator that can efficiently generate a highly dynamic S-box with good cryptographic properties is a hot topic in the field of cryptography. Recently, elliptic curve (EC)-based S-box generators have shown promising results. However, these generators use large ECs to generate highly dynamic S-boxes and thus may not be suitable for lightweight cryptography, where the computational power is limited. The aim of this paper is to develop and implement such an S-box generator that can be used in lightweight cryptography and perform better in terms of computation time and security resistance than recently designed S-box generators. To achieve this goal, we use ordered ECs of small size and binary sequences to generate certain sequences of integers which are then used to generate S-boxes. We performed several standard analyses to test the efficiency of the proposed generator. On an average, the proposed generator can generate an S-box in 0.003 seconds, and from 20,000 S-boxes generated by the proposed generator, 93 % S-boxes have at least the nonlinearity 96. The linear approximation probability of 1000 S-boxes that have the best nonlinearity is in the range [0.117, 0.172] and more than 99% S-boxes have algebraic complexity at least 251. All these S-boxes have the differential approximation probability value in the interval [0.039, 0.063]. Computational results and comparisons suggest that our newly developed generator takes less running time and has high security against modern attacks as compared to several existing well-known generators, and hence, our generator is suitable for lightweight cryptography. Furthermore, the usage of binary sequences in our generator allows generating plaintext-dependent S-boxes which is crucial to resist chosen-plaintext attacks.

A new color image encryption technique using DNA computing and Chaos-based substitution box

In many cases, images contain sensitive information and patterns that require secure processing to avoid risk. It can be accessed by unauthorized users who can illegally exploit them to threaten the safety of people’s life and property. Protecting the privacies of the images has quickly become one of the biggest obstacles that prevent further exploration of image data. In this paper, we propose a novel privacy-preserving scheme to protect sensitive information within images. The proposed approach combines deoxyribonucleic acid (DNA) sequencing code, Arnold transformation (AT), and a chaotic dynamical system to construct an initial S-box. Various tests have been conducted to validate the randomness of this newly constructed S-box. These tests include National Institute of Standards and Technology (NIST) analysis, histogram analysis (HA), nonlinearity analysis (NL), strict avalanche criterion (SAC), bit independence criterion (BIC), bit independence criterion strict avalanche criterion (BIC-SAC), bit independence criterion nonlinearity (BIC-NL), equiprobable input/output XOR distribution, and linear approximation probability (LP). The proposed scheme possesses higher security wit NL = 103.75, SAC ≈ 0.5 and LP = 0.1560. Other tests such as BIC-SAC and BIC-NL calculated values are 0.4960 and 112.35, respectively. The results show that the proposed scheme has a strong ability to resist many attacks. Furthermore, the achieved results are compared to existing state-of-the-art methods. The comparison results further demonstrate the effectiveness of the proposed algorithm.

FPGA Implementation of Protected Compact AES S–Box Using CQCG for Embedded Applications

In this work, we obtain an area proficient composite field arithmetic Advanced Encryption Standard (AES) Substitution (S) byte and its inverse logic design. The size of this design is calculated by the number of gates used for hardware implementation. Most of the existing AES Substitution box hardware implementation uses separate Substitution byte and its inverse hardware structures. But we implement the both in the same module and a control signal is used to select the substitution byte for encryption operation and its inverse for the decryption operation. By comparing the gate utilization of the previous AES S–Box implementation, we reduced the gate utilization up to 5% that is we take only 78 EX-OR gates and 36 AND gates for implementing the both Substitution byte and its inverse. While implementing an AES algorithm in circuitry or programming, it is liable to be detected by hackers using any one of the side channel attacks. Data to be added with a random bit sequence to prevent from the above mentioned side channel attacks.

DYNAMIC SUBSTITUTION BOXES OF SYMMETRIC BLOCK ENCRYPTION ALGORITHMS

The paper deals with nonlinear transformations of well-known symmetric block algorithms such as AES, Kuznyechik, SM4, BelT, and Kalyna. A brief description of the substitution boxes for these algorithms is given. The properties of nonlinearity of the described substitution boxes are investigated with the calculation of the corresponding values. Based on the property of nonlinearity, a method for generating a dynamic substitution box is proposed. The purpose of this method is to generate dynamic substitution boxes (S-boxes) that change depending on the values of some parameter obtained from the secret key of the algorithm. Considering that linear and differential cryptanalysis uses known substitution boxes, the main advantage of the new method is that S-boxes are randomly key-dependent and unknown. Experiments were also carried out to implement this method. The resulting dynamic substitution boxes were tested for nonlinearity and the results were compared with the original nonlinearity values of the same substitution boxes.

Speech Encryption Technique using S - box based on Multi Chaotic Maps

This paper proposes the establishment of a secure encryption system for data transmission that includes three stages: first stage is a scrambling stage that is divided into scrambling of different sizes blocks and scrambling bits, the second stage is the use of DNA code to flip the bits and the third stage is the encryption using the Substitution box by 256 keys. The scheme is analysed using a variety of metrics. The findings demonstrate that the proposed system is significantly more reliable and robust against various forms of attacks than several recent related speech signal encryption systems.

The SPEEDY Family of Block Ciphers

We introduce SPEEDY, a family of ultra low-latency block ciphers. We mix engineering expertise into each step of the cipher’s design process in order to create a secure encryption primitive with an extremely low latency in CMOS hardware. The centerpiece of our constructions is a high-speed 6-bit substitution box whose coordinate functions are realized as two-level NAND trees. In contrast to other low-latency block ciphers such as PRINCE, PRINCEv2, MANTIS and QARMA, we neither constrain ourselves by demanding decryption at low overhead, nor by requiring a super low area or energy. This freedom together with our gate- and transistor-level considerations allows us to create an ultra low-latency cipher which outperforms all known solutions in single-cycle encryption speed. Our main result, SPEEDY-6-192, is a 6-round 192-bit block and 192-bit key cipher which can be executed faster in hardware than any other known encryption primitive (including Gimli in Even-Mansour scheme and the Orthros pseudorandom function) and offers 128-bit security. One round more, i.e., SPEEDY-7-192, provides full 192-bit security. SPEEDY primarily targets hardware security solutions embedded in high-end CPUs, where area and energy restrictions are secondary while high performance is the number one priority.