scholarly journals FPGA Implementation of Protected Compact AES S–Box Using CQCG for Embedded Applications

2021 ◽  
Author(s):  
R. Sornalatha ◽  
N. Janakiraman ◽  
K. Balamurugan ◽  
Arun Kumar Sivaraman ◽  
Rajiv Vincent ◽  
...  
Keyword(s):  
Hardware Implementation ◽  
Fpga Implementation ◽  
Advanced Encryption Standard ◽  
Side Channel ◽  
Logic Design ◽  
Substitution Box ◽  
Side Channel Attacks ◽  
Aes Algorithm ◽  
Composite Field ◽  
Embedded Applications

In this work, we obtain an area proficient composite field arithmetic Advanced Encryption Standard (AES) Substitution (S) byte and its inverse logic design. The size of this design is calculated by the number of gates used for hardware implementation. Most of the existing AES Substitution box hardware implementation uses separate Substitution byte and its inverse hardware structures. But we implement the both in the same module and a control signal is used to select the substitution byte for encryption operation and its inverse for the decryption operation. By comparing the gate utilization of the previous AES S–Box implementation, we reduced the gate utilization up to 5% that is we take only 78 EX-OR gates and 36 AND gates for implementing the both Substitution byte and its inverse. While implementing an AES algorithm in circuitry or programming, it is liable to be detected by hackers using any one of the side channel attacks. Data to be added with a random bit sequence to prevent from the above mentioned side channel attacks.

scholarly journals Eluding Side Channel Attacks by using Masking 128Bit AES Design

2020 ◽  
Vol 9 (8) ◽  
pp. 952-955
Keyword(s):  
Data Transmission ◽  
Advanced Encryption Standard ◽  
Side Channel ◽  
Side Channel Attacks ◽  
Equal Area ◽  
Original Algorithm ◽  
Aes Algorithm ◽  
Side Channels ◽  
Standard Design ◽  
Secure Data Transmission

: Advanced encryption standard is detailing for data crypto graphing. The algorithm used universally for cryptography and secure data transmission, the algorithm puissant to intruders, who often attack via side channels. One of the observed attacks was estimate the power implanted in AES core and processed probable scrutinizing to guess the key on multiple iterations. So in order to elude side channel attacks and reduce power consumed in AES standard, design proposed with masking and pipeline scheme. This design helps in shrinking power consumption as compare to AES algorithm and upgrade to withstand from attacks. Another major improvement in the design is LUT’s used for masking and original algorithm almost equal, area phenomenon also solved out. The proposed algorithm implemented in VERTEX-7 FPGA board and simulated using Xilinx Vivado 2015.2 and Modelsim.

CompactRIO Based Real Time Implementation of AES Algorithm for Embedded Applications

2019 ◽  
Vol 10 (2) ◽  
pp. 19-36
Author(s):  
El Adib Samir ◽  
Raissouni Naoufal
Keyword(s):  
Power Consumption ◽  
Real Time ◽  
Software Design ◽  
System Architecture ◽  
Advanced Encryption Standard ◽  
Time Cost ◽  
Security Applications ◽  
Aes Algorithm ◽  
Embedded Applications ◽  
Different Levels

For real-time embedded applications, several factors (time, cost, power) that are moving security considerations from a function-centric perspective into a system architecture (hardware/software) design issue. The National Institute of Standards and Technology (NIST) adopts Advanced Encryption Standard (AES) as the most widely used encryption algorithm in many security applications. The AES algorithm specifies 10, 12 and 14 rounds offering different levels of security. Although the number of rounds determines the strength of security, the power consumption issue has risen recently, especially in real-time embedded systems. In this article, the authors present real time implementation of the AES encryption on the compactRIO platform for a different number of AES rounds. The target hardware is NI cRIO-9022 embedded real-time controller from National Instruments (NI). The real time encryption processing has been verified successfully. The power consumption and encryption time experimental results are presented graphically for 10, 12 and 14 rounds of processing.

Very Compact and Efficient 32-Bit AES Core Design Using FPGAs for Small-Footprint Low-Power Embedded Applications

2016 ◽  
Vol 25 (07) ◽  
pp. 1650080 ◽  
Author(s):  
Raed Bani-Hani ◽  
Khaldoon Mhaidat ◽  
Salah Harb
Keyword(s):  
Low Power ◽  
Area Ratio ◽  
Advanced Encryption Standard ◽  
Fpga Design ◽  
Power Efficient ◽  
Aes Algorithm ◽  
Lookup Tables ◽  
Small Footprint ◽  
Embedded Applications

In this paper, a very compact and efficient 32-bit FPGA design for the Advanced Encryption Standard (AES) algorithm is presented. The design is very well suited for small foot-print low-power embedded applications. The design is validated and synthesized using the Xilinx ISE Design Suite. To the best of our knowledge, our design is the most efficient in terms of throughput to area ratio and requires the smallest number of lookup tables (LUTs), logic slices, and registers. It also achieves the highest throughput among designs that do not use DSPs. It is also very power-efficient; it can process more than 10 Gbps/W on Kintex-7 FPGA.

PERFORMANCE CHARACTERIZATION OF PIPELINED S-BOX IMPLEMENTATIONS FOR THE ADVANCED ENCRYPTION STANDARD

2014 ◽  
Vol 23 (03) ◽  
pp. 1450036
Author(s):  
CHENG WANG ◽  
HOWARD M. HEYS
Keyword(s):  
Performance Improvement ◽  
Cmos Technology ◽  
Field Structure ◽  
Advanced Encryption Standard ◽  
Substitution Box ◽  
Component Level ◽  
Comprehensive Investigation ◽  
Fine Grained ◽  
Composite Field

In this paper, we present a comprehensive investigation of the influence of pipeline configurations on the performance of ASIC implementations of the Advanced Encryption Standard (AES) substitution box (S-box) based on a composite field structure. We consider pipeline configurations for the S-box with a typical composite field structure by varying the number of pipeline stages and the placement approach of pipeline registers. Besides the conventional placement approach at the component level of the S-box, we adopt a new placement approach at the gate level to achieve a fine-grained pipeline. The performance of the pipelined S-boxes is characterized based on a 90-nm standard cell CMOS technology. The characterization shows that there is notable performance improvement in timing, area, power and/or energy efficiency by using an appropriate configuration compared with other configurations including non-pipelined implementations. These results are strong evidence that pipelined S-box implementations are not only suitable for high throughput AES implementations, but also valuable to resource-efficient AES implementations. In addition, it is also shown that pipelining provides many more performance options that allow more flexible implementation of the AES S-box compared with non-pipelined implementations.

Iterative and Fully Pipelined High Throughput Efficient Architectures of AES in FPGA and ASIC

2016 ◽  
Vol 25 (05) ◽  
pp. 1650049 ◽  
Author(s):  
Vijay K. Sharma ◽  
Saurabh Kumar ◽  
K. K. Mahapatra
Keyword(s):  
High Throughput ◽  
Unit Area ◽  
Critical Path ◽  
Advanced Encryption Standard ◽  
Vlsi Architectures ◽  
Aes Algorithm ◽  
Composite Field ◽  
Low Energy Consumption ◽  
Field Programmable ◽  
Hardware Efficiency

This paper presents high throughput iterative and pipelined VLSI architectures of the Advanced encryption standard (AES) algorithm based on composite field arithmetic in polynomial basis. A logical rearrangement has been performed in the byte substitution (S-box) module to reduce the number of gates in the critical path. Also, inversion in GF(24) module has been separately optimized. ASIC implementation of our S-box has comparatively low power and low energy consumption. The iterative and pipelined implementations of AES in field programmable gate array (FPGA) and ASIC using proposed S-box have high hardware efficiency in terms of throughput per unit area (slices in FPGA).

The Hardware Implementation of a Lightweight Block Cipher Algorithm and a Message Authentication Algorithm

2012 ◽  
Vol 546-547 ◽  
pp. 1489-1494
Author(s):  
Yi Kun Hu ◽  
Zun Yang Qin
Keyword(s):  
Hardware Implementation ◽  
Block Cipher ◽  
Side Channel ◽  
Message Authentication ◽  
Side Channel Attack ◽  
Side Channel Attacks ◽  
Processing Efficiency ◽  
New Family ◽  
Lightweight Block Cipher ◽  
Lightweight Cipher

Among the block cipher algorithms, AES or DES is an excellent and preferred choice for most block cipher applications. But AES and DES are not very suitable for hardware implementation because of the high cost that they require large areas of routing and the processing efficiency is low, relatively. So lightweight cipher algorithms come into beings, among which PRESENT is very competitive. Along with the structure of a message authentication algorithm ALRED, a new family of Tunable Lightweight MAC based on PRESENT is proposed, that is TuLP. However, PRESENT is not able to resist side channel attack, so is TuLP, of course. For the above reason, in this paper, we provide an improvement of PRESENT by inserting random dummy cycles as well as shuffling to strengthen the security of PRESENT against side channel attacks. We will implement PRESENT and TuLP in Verilog and do simulation on Xilinx ISim platform. At last, we would like to provide the power analyzing of Xilinx XPower.

scholarly journals Exploiting Small Leakages in Masks to Turn a Second-Order Attack into a First-Order Attack and Improved Rotating Substitution Box Masking with Linear Code Cosets

2015 ◽  
Vol 2015 ◽  
pp. 1-10 ◽  
Author(s):  
Alexander DeTrano ◽  
Naghmeh Karimi ◽  
Ramesh Karri ◽  
Xiaofei Guo ◽  
Claude Carlet ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
State Of The Art ◽  
Second Order ◽  
Advanced Encryption Standard ◽  
Secret Key ◽  
Noisy Environment ◽  
Substitution Box ◽  
First Order ◽  
Aes Algorithm ◽  
Low Entropy

Masking countermeasures, used to thwart side-channel attacks, have been shown to be vulnerable to mask-extraction attacks. State-of-the-art mask-extraction attacks on the Advanced Encryption Standard (AES) algorithm target S-Box recomputation schemes but have not been applied to scenarios where S-Boxes are precomputed offline. We propose an attack targeting precomputed S-Boxes stored in nonvolatile memory. Our attack targets AES implemented in software protected by a low entropy masking scheme and recovers the masks with 91% success rate. Recovering the secret key requires fewer power traces (in fact, by at least two orders of magnitude) compared to a classical second-order attack. Moreover, we show that this attack remains viable in a noisy environment or with a reduced number of leakage points. Eventually, we specify a method to enhance the countermeasure by selecting a suitable coset of the masks set.

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