Reducing energy consumption using data encoding techniques in network on chip

2014 ◽  
Author(s):  
S. Senthamil ◽  
P. Saravanakumar
Keyword(s):  
Energy Consumption ◽  
Network On Chip ◽  
Data Encoding ◽  
Using Data ◽  
On Chip ◽  
Reducing Energy

Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip

2014 ◽  
Vol 22 (3) ◽  
pp. 675-685 ◽  
Author(s):  
Nima Jafarzadeh ◽  
Maurizio Palesi ◽  
Ahmad Khademzadeh ◽  
Ali Afzali-Kusha
Keyword(s):  
Energy Consumption ◽  
Network On Chip ◽  
Data Encoding ◽  
On Chip ◽  
Reducing Energy

Research on Network-on-Chip Dynamic and Adaptive Algorithm and Choice Strategy

2014 ◽  
Vol 539 ◽  
pp. 296-302
Author(s):  
Dong Li
Keyword(s):  
Energy Consumption ◽  
Execution Time ◽  
Adaptive Algorithm ◽  
Network On Chip ◽  
Time Dimension ◽  
Choice Strategy ◽  
Bus Structure ◽  
On Chip ◽  
Mapping Scheme ◽  
Single Objective

With further increase of the number of on-chip device, the bus structure has not met the requirements. In order to make better communication between each part, the chip designers need to explore a new structure to solve the interconnection of on-chip device. The paper proposes a network-on-chip dynamic and adaptive algorithm which selects NoC platform with 2-dimension mesh as the carrier, incorporates communication energy consumption and delay into unified cost function and uses ant colony optimization to realize NOC map facing energy consumption and delay. The experiment indicates that compared with random map, single objective optimization can separately saves (30%~47 %) and ( 20%~39%) in communication energy consumption and execution time compared with random map, and joint objective optimization can further excavate the potential of time dimension in mapping scheme dominated by the energy.

Comparison of network-on-chip mapping algorithms targeting low energy consumption

2008 ◽  
Vol 2 (6) ◽  
pp. 471 ◽  
Author(s):  
C.A.M. Marcon ◽  
E.I. Moreno ◽  
N.L.V. Calazans ◽  
F.G. Moraes
Keyword(s):  
Energy Consumption ◽  
Network On Chip ◽  
Low Energy ◽  
Mapping Algorithms ◽  
Low Energy Consumption ◽  
On Chip

scholarly journals Parallel Applications Mapping onto Network on Chip Based on Heterogeneous MPSoCs Using Hybrid Algorithms

2019 ◽  
Vol 10 (2) ◽  
pp. 37-63
Author(s):  
Dihia Belkacemi ◽  
Mehammed Daoui ◽  
Samia Bouzefrane ◽  
Youcef Bouchebaba
Keyword(s):  
Energy Consumption ◽  
Population Based ◽  
Network On Chip ◽  
Hybrid Algorithms ◽  
Parallel Applications ◽  
High Quality ◽  
Multi Objective ◽  
Hybrid Solutions ◽  
Single Solution ◽  
On Chip

Mapping parallel applications onto a network on chip (NoC) that is based on heterogeneous MPSoCs is considered as an instance of an NP-hard and a multi-objective problem. Various multi-objective algorithms have been proposed in the literature to handle this issue. Metaheuristics stand out as highly appropriate approaches to deal with this kind of problem. These metaheuristics are classified into two sets: population-based metaheuristics and single solution-based ones. To take advantage of the both sets, the trend is to use hybrid solutions that have shown to give better results. In this article, the authors propose to hybridize these two metaheuristics sets to find good Pareto mapping solutions to optimize the execution time and the energy consumption simultaneously. The experimental results have shown that the proposed hybrid algorithms give high quality non-dominated mapping solutions in a reasonable runtime.

scholarly journals Validation of Hybrid Network-on-Chip Architecture for Optimized Performance using BookSim Simulator

2020 ◽  
Vol 8 (6) ◽  
pp. 3393-3397
Keyword(s):  
Energy Consumption ◽  
Integrated Circuits ◽  
Spread Spectrum ◽  
Direct Sequence Spread Spectrum ◽  
Network On Chip ◽  
Hybrid Network ◽  
Direct Sequence ◽  
Packet Latency ◽  
On Chip ◽  
The Cost

Various complex integrated circuits suffer from the issues like poor connectivity, higher energy consumption and design productivity. One of the best solutions could be Network-on-Chip architecture which could solve the above issues. The Network-on-Chip architecture should be modelled and simulated well to evaluate the performance and analyse the cost. This paper presents a method to validate the proposed Network-on-Chip architecture with direct sequence spread spectrum using BookSim simulator. This simulation aims at validating the network parameters like packet latency and network latency. The detailed architectural parameters are compared and presented in this paper.

scholarly journals Congestion-Aware Routing Algorithm for NoC Using Data Packets

2021 ◽  
Vol 2021 ◽  
pp. 1-11
Author(s):  
Khurshid Ahmad ◽  
Muhammad Athar Javed Sethi ◽  
Rehmat Ullah ◽  
Imran Ahmed ◽  
Amjad Ullah ◽  
...  
Keyword(s):  
Routing Algorithm ◽  
Network On Chip ◽  
Routing Algorithms ◽  
System On Chip ◽  
Multiprocessor System ◽  
Data Packets ◽  
Communication Framework ◽  
Using Data ◽  
On Chip ◽  
Congestion Aware

Network on Chip (NoC) is a communication framework for the Multiprocessor System on Chip (MPSoC). It is a router-based communication system. In NoC architecture, nodes of MPSoC are communicating through the network. Different routing algorithms have been developed by researchers, e.g., XY, intermittent XY, DyAD, and DyXY. The main problems in these algorithms are congestion and faults. Congestion and faults cause delay, which degrades the performance of NoC. A congestion-aware algorithm is used for the distribution of traffic over NoC and for the avoidance of congestion. In this paper, a congestion-aware routing algorithm is proposed. The algorithm works by sending congestion information in the data packet. The algorithm is implemented on a 4 × 4 mesh NoC using FPGA. The proposed algorithm decreases latency, increases throughput, and uses less bandwidth in sharing congestion information between routers in comparison to the existing congestion-aware routing algorithms.

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