Congestion-Aware Routing Algorithm for NoC Using Data Packets

Network on Chip (NoC) is a communication framework for the Multiprocessor System on Chip (MPSoC). It is a router-based communication system. In NoC architecture, nodes of MPSoC are communicating through the network. Different routing algorithms have been developed by researchers, e.g., XY, intermittent XY, DyAD, and DyXY. The main problems in these algorithms are congestion and faults. Congestion and faults cause delay, which degrades the performance of NoC. A congestion-aware algorithm is used for the distribution of traffic over NoC and for the avoidance of congestion. In this paper, a congestion-aware routing algorithm is proposed. The algorithm works by sending congestion information in the data packet. The algorithm is implemented on a 4 × 4 mesh NoC using FPGA. The proposed algorithm decreases latency, increases throughput, and uses less bandwidth in sharing congestion information between routers in comparison to the existing congestion-aware routing algorithms.

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YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAs

Journal of Circuits System and Computers ◽

10.1142/s0218126619502025 ◽

2019 ◽

Vol 28 (12) ◽

pp. 1950202 ◽

Cited By ~ 2

Author(s):

Khyamling Parane ◽

B. M. Prabhu Prasad ◽

Basavaraj Talawar

Keyword(s):

Design Space Exploration ◽

Routing Algorithm ◽

Adaptive Routing ◽

Network On Chip ◽

Routing Algorithms ◽

Tree Topology ◽

Traffic Pattern ◽

Mesh Topology ◽

On Chip ◽

Congestion Aware

Many-core systems employ the Network on Chip (NoC) as the underlying communication architecture. To achieve an optimized design for an application under consideration, there is a need for fast and flexible NoC simulator. This paper presents an FPGA-based NoC simulation acceleration framework supporting design space exploration of standard and custom NoC topologies considering a full set of microarchitectural parameters. The framework is capable of designing custom routing algorithms, various traffic patterns such as uniform random, transpose, bit complement and random permutation are supported. For conventional NoCs, the standard minimal routing algorithms are supported. For designing the custom topologies, the table-based routing has been implemented. A custom topology called diagonal mesh has been evaluated using table-based and novel shortest path routing algorithm. A congestion-aware adaptive routing has been proposed to route the packets along the minimally congested path. The congestion-aware adaptive routing algorithm has negligible FPGA area overhead compared to the conventional XY routing. Employing the congestion-aware adaptive routing, network latency is reduced by 55% compared to the XY routing algorithm. The microarchitectural parameters such as buffer depth, traffic pattern and flit width have been varied to observe the effect on NoC behavior. For the [Formula: see text] mesh topology, the LUT and FF usages will be increased from 32.23% to 34.45% and from 12.62% to 15% considering the buffer depth of 4 and flit widths of 16 bits, and 32 bits, respectively. Similar behavior has been observed for other configurations of buffer depth and flit width. The torus topology consumes 24% more resources than the mesh topology. The 56-node fat tree topology consumes 27% and 2.2% more FPGA resources than the [Formula: see text] mesh and torus topologies. The 56-node fat tree topology with buffer depth of 8 and 16 flits saturates at the injection rates of 40% and 45%, respectively.

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Reliable Weighted Globally Congestion Aware Routing for Network on Chip

International Journal of Embedded and Real-Time Communication Systems ◽

10.4018/ijertcs.2020070103 ◽

2020 ◽

Vol 11 (3) ◽

pp. 48-66

Author(s):

Habib Chawki Touati ◽

Fateh Boutekkouk

Keyword(s):

State Of The Art ◽

Network On Chip ◽

Routing Algorithms ◽

Single Chip ◽

Transmission Delays ◽

Data Packets ◽

Fully Adaptive ◽

On Chip ◽

Propagation Network ◽

Congestion Aware

With the ability to incorporate hundreds of communicating cores on a single chip, thanks to the continuous shrinkage in sizes, communication became of the utmost importance. Consequently, the reduction of transmission delays became unavoidably necessary. All of which is achieved by means of routing algorithms, responsible for selecting the most appropriate routes for data packets, by avoiding congested regions in the network between any pair of source and destination nodes. In this article, two moderately distinct versions in terms of weight distribution of a minimal, fully adaptive, congestion-aware routing scheme in mesh-based network on chip and its accompanying congestion propagation network, are presented. The algorithm does not rely solely on local congestion information nor on irrelevant global information, and provides somewhat a compromise between locally and globally aware routing. The experimental results showcase the proposed scheme's superiority over state of the art NoC routing algorithms.

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A congestion-aware routing algorithm for simplified mesh-of-tree architecture in network-on-chip designs

Artificial Intelligence and Industrial Application ◽

10.2495/aiia140551 ◽

2015 ◽

Author(s):

J. Fang ◽

L. Yu ◽

Z. Y. Leng

Keyword(s):

Routing Algorithm ◽

Network On Chip ◽

Tree Architecture ◽

On Chip ◽

Congestion Aware

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Design of Router Supporting Multiply Routing Algorithm for NoC

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.981.431 ◽

2014 ◽

Vol 981 ◽

pp. 431-434

Author(s):

Zhan Peng Jiang ◽

Rui Xu ◽

Chang Chun Dong ◽

Lin Hai Cui

Keyword(s):

Complex System ◽

High Performance ◽

Routing Algorithm ◽

Network On Chip ◽

System On Chip ◽

Low Latency ◽

Deterministic Routing ◽

Key Features ◽

Design Challenge ◽

On Chip

Network on Chip(NoC)，a new proposed solution to solve global communication problem in complex System on Chip (SoC) design，has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus，and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

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Comparative Performance Analysis of  Selected Routing Algorithms by Load Variation of 2-Dimensional Mesh Topology Based  Network-On-Chip

ELEKTRIKA- Journal of Electrical Engineering ◽

10.11113/elektrika.v20n3.249 ◽

2021 ◽

Vol 20 (3) ◽

pp. 1-6

Author(s):

Mohammed Shaba Saliu ◽

Muyideen Omuya Momoh ◽

Pascal Uchenna Chinedu ◽

Wilson Nwankwo ◽

Aliu Daniel

Keyword(s):

Routing Algorithm ◽

Adaptive Routing ◽

Injection Rate ◽

Network On Chip ◽

Routing Algorithms ◽

Comparative Performance ◽

Traffic Pattern ◽

Mesh Topology ◽

Similar Vein ◽

On Chip

Network-on-Chip (NoC) has been proposed as a viable solution to the communication challenges on System-on-Chips (SoCs). As the communication paradigm of SoC, NoCs performance depends mainly on the type of routing algorithm chosen. In this paper different categories of routing algorithms were compared. These include XY routing, OE turn model adaptive routing, DyAD routing and Age-Aware adaptive routing. By varying the load at different Packet Injection Rate (PIR) under random traffic pattern, comparison was conducted using a 4 × 4 mesh topology. The Noxim simulator, a cycle accurate systemC based simulator was employed. The packets were modeled as a Poisson distribution; first-in-first-out (FIFO) input buffer channel with a depth of five (5) flits and a flit size of 32 bits; and a packet size of 3 flits respectively. The simulation time was 10,000 cycles. The findings showed that the XY routing algorithm performed better when the PIR is low. In a similar vein, the DyAD routing and Age-aware algorithms performed better when the load i.e. PIR is high.

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