VHDL implementation of an optimized 8-point FFT/IFFT processor in pipeline architecture for OFDM systems

Author(s):  
Mounir Arioua ◽  
Said Belkouch ◽  
Mohamed Agdad ◽  
Moha M'rabet Hassani
2012 ◽  
Vol 588-589 ◽  
pp. 826-829
Author(s):  
Xiang Bin Meng ◽  
Jin Xiang Wang ◽  
Hai Long Yan

An attractive technique of variable-length Fast Fourier transform (FFT) processor is proposed for PAPR reduction in orthogonal frequency division multiplexing (OFDM) systems. Mixed-radix algorithm and single path delay feedback (SDF) pipeline architecture is adopted to obtain low computation complexity and preferable flexibility for its VLSI implementation. The FFT processor can be reconfigured as 512, 1024, 2048, 4096-points, moreover, the only one RAM unit is used for store sine/cosine tables. The chip is mapped to the 0.18 CMOS technology and the core area is 7.896mm2. The experiment results show that the proposed FFT processor is suitable for PAPR reduction in OFDM communication systems.


2011 ◽  
Vol E94-B (12) ◽  
pp. 3614-3617
Author(s):  
Bin SHENG ◽  
Pengcheng ZHU ◽  
Xiaohu YOU

2018 ◽  
Vol E101.B (11) ◽  
pp. 2320-2330
Author(s):  
Yong DING ◽  
Shan OUYANG ◽  
Yue-Lei XIE ◽  
Xiao-Mao CHEN
Keyword(s):  

2018 ◽  
Vol E101.B (3) ◽  
pp. 856-864 ◽  
Author(s):  
Moeko YOSHIDA ◽  
Hiromichi NASHIMOTO ◽  
Teruyuki MIYAJIMA

2012 ◽  
Vol E95.B (9) ◽  
pp. 2926-2930
Author(s):  
Qinjuan ZHANG ◽  
Muqing WU ◽  
Qilin GUO ◽  
Rui ZHANG ◽  
Chao Yi ZHANG

Sign in / Sign up

Export Citation Format

Share Document