scholarly journals Analysis of Interconnection Networks in Heterogeneous Multi-Cluster Systems

2006 ◽  
Author(s):  
B. Javadi ◽  
J.H. Abawajy ◽  
M.K. Akbari ◽  
S. Nahavandi
Keyword(s):  
Interconnection Networks ◽  
Cluster Systems

scholarly journals Performance Analysis of Interconnection Networks for Multi-cluster Systems

2005 ◽  
pp. 205-212 ◽  
Author(s):  
Bahman Javadi ◽  
J. H. Abawajy ◽  
Mohammad K. Akbari
Keyword(s):  
Performance Analysis ◽  
Interconnection Networks ◽  
Cluster Systems

A comprehensive analytical model of interconnection networks in large-scale cluster systems

2007 ◽  
Vol 20 (1) ◽  
pp. 75-97 ◽  
Author(s):  
Bahman Javadi ◽  
Jemal H. Abawajy ◽  
Mohammad K. Akbari
Keyword(s):  
Analytical Model ◽  
Interconnection Networks ◽  
Large Scale ◽  
Cluster Systems

Analytical modeling of interconnection networks in heterogeneous multi-cluster systems

2007 ◽  
Vol 40 (1) ◽  
pp. 29-47 ◽  
Author(s):  
Bahman Javadi ◽  
Jemal H. Abawajy ◽  
Mohammad K. Akbari
Keyword(s):  
Interconnection Networks ◽  
Analytical Modeling ◽  
Cluster Systems

Logistics management in shipbuilding cluster systems

2014 ◽  
Vol 0 (3) ◽  
Author(s):  
Mykola V. Fatieiev ◽  
Iryna M. Zaporozhets
Keyword(s):  
Logistics Management ◽  
Cluster Systems

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

Quantitative Reliability Analysis of Redundant Multistage Interconnection Networks

1991 ◽  
Author(s):  
Nita M. Kini ◽  
Anup Kumar ◽  
Dharma P. Agrawal
Keyword(s):  
Reliability Analysis ◽  
Interconnection Networks ◽  
Multistage Interconnection Networks

Concurrent error detection in VLSI interconnection networks

1983 ◽  
Vol 11 (3) ◽  
pp. 309-315 ◽  
Author(s):  
W. Kent Fuchs ◽  
Jacob A. Abraham ◽  
Kuang-Hua Huang
Keyword(s):  
Error Detection ◽  
Interconnection Networks ◽  
Concurrent Error Detection
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