PWM strategy of single-phase to three-phase matrix converters for reducing output voltage harmonics and number of commutations

Author(s):  
Yusuke Furuhashi ◽  
Takaharu Takeshita
2019 ◽  
Vol 139 (11) ◽  
pp. 901-907
Author(s):  
Jumpei Sawada ◽  
Shin-ichi Motegi ◽  
Yoshitaka Nakamura ◽  
Masaki Yamada

Author(s):  
G. Vijaykrishna ◽  
Y. Kusumalatha

This paper examines how a Reversing voltage multilevel inverter (RVMLI) strategy is enforced to develop multilevel inverter fulfilment. This approach has been used SPWM-PD technique to regulate the electrical inverter. It desires numerous less range of carrier signals to deliver gate pulses of switches. Increasing within the levels during this strategy aid in reduction of output voltage harmonics expeditiously and improves power quality at output of the electrical inverter. It wants a lowered quantity of total switches, which is in a position to decreases of switching losses in this process. The Three-phase reversing voltage multilevel inverter of 7- level and 9- level is accomplished for R-load and R-L load and Three Phase Induction Motor. A reversing voltage multilevel inverter of 7- level and 9- level simulation is intended and developed. Mat lab/Simulink outcome is awarded to validate the proposed scheme.


1975 ◽  
Vol 12 (1) ◽  
pp. 44-56 ◽  
Author(s):  
I. R. Smith ◽  
S. Williams

An analysis is presented of inductively-loaded single-phase and three-phase thyristor bridge rectifier circuits, in which the source impedance cannot be neglected. It is shown that, as the ratio of the source reactance to the load resistance is raised, modes of operation with differing characteristics occur. Although the effect of an increased delay in the thyristor firing signals is normally to reduce the output voltage, it is shown that under certain conditions no change whatsoever is produced in the circuit wave-forms.


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