A fast VLSI architecture for two-dimensional discrete wavelet transform based on lifting scheme

2005 ◽  
Author(s):  
Chengyi Xiong ◽  
Jinwen Tian ◽  
Jian Liu
Keyword(s):  
Wavelet Transform ◽  
Discrete Wavelet Transform ◽  
Vlsi Architecture ◽  
Lifting Scheme ◽  
Discrete Wavelet ◽  
Two Dimensional

A VLSI Architecture of 2-D Discrete Wavelet Transform for Reducing Computation Time

2013 ◽  
Vol 284-287 ◽  
pp. 2463-2467
Author(s):  
Chin Fa Hsieh ◽  
Tsung Han Tsai ◽  
Cheng Chung Liu
Keyword(s):  
Wavelet Transform ◽  
Discrete Wavelet Transform ◽  
Traditional Method ◽  
Computing Time ◽  
Vlsi Architecture ◽  
Computation Time ◽  
Original Data ◽  
Discrete Wavelet ◽  
Two Dimensional

In this paper, we propose an efficient VLSI architecture for implementing the forward two-dimensional discrete wavelet transform (2D DWT), which is computed without utilizing the traditional method of rows-by-columns or columns-by-rows. On account of the relation form within the original data, we apply masks of different window sizes to the transform and design the architecture based on these different window masks. On the comparison of the computing time, the proposed architecture requires only N*N/4 clock cycles for an N*N image, while it takes N*N clock cycles for the traditional row-by-column/column-by-row 2D DWT. The proposed architecture has a better performance than other designs reported in the literature.

FPGA Implementation of a High-Speed Two Dimensional Discrete Wavelet Transform

2013 ◽  
Vol 479-480 ◽  
pp. 508-512
Author(s):  
Chin Fa Hsieh ◽  
Tsung Han Tsai
Keyword(s):  
Wavelet Transform ◽  
Discrete Wavelet Transform ◽  
Real Time ◽  
High Speed ◽  
Critical Path ◽  
Vlsi Architecture ◽  
Image Sensor ◽  
Discrete Wavelet ◽  
Two Dimensional ◽  
Clock Period

This paper proposes high-speed VLSI architecture for implementing a forward two-dimensional discrete wavelet transform (2D DWT). The architecture is based on 2D DWT mathematical formulae. A pipelined scheme is used to increase the clock rate, which allows its critical path to take only one adder delay. The proposed design enables 100% hardware use and faster computing than other 2D DWT architecture. It is easily extended to multilevel decomposition because of its regular structure. It requires N/2 by N/2 clock cycles for k-level analysis of an N by N image. The proposed architecture was coded in VerilogHDL and verified on a real time platform which uses a CMOS image sensor, a field-programmable gate array (FPGA) and a TFT-LCD panel. In the simulation, the design worked with a clock period of 132.38MHz. It can be used as an independent IP core for various real-time applications.

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