Multi-collector ECL circuit family and its application to 1 GHz prescaler IC

Author(s):  
S. Shimizu ◽  
S. Komatsu ◽  
K. Torii
Keyword(s):  
Author(s):  
Senthil C. Pari

The objective of this chapter is to describe the various designed arithmetic circuit for an application of multimedia circuit that can be used in a high-performance or mobile microprocessor with a particular set of optimisation criteria. The aim of this chapter is to describe the design method of binary arithmetic especially using by CMOS and Pass Transistor Logic technique. The pass transistor techniques are reduced the noise margin for small circuit, which can be explained in this chapter. This chapter further describe the types of arithmetic and its techniques. The technique design principle procedure should make the following decisions: circuit family (complementary static CMOS, pass-transistor, or Shannon Theorem based); type of arithmetic to be used. The decisions on the designed logic level significantly affect the propagation delay, area and power dissipation.


Author(s):  
N.J. Shin ◽  
P.F. Lu ◽  
C.T. Chuang
Keyword(s):  

Author(s):  
A. Solomatnikov ◽  
D. Somasekhar ◽  
N. Sirisantana ◽  
K. Roy

Author(s):  
A.J. Fixl ◽  
K.A. Jenkins ◽  
K.R. Wilsher ◽  
M.J. Immediato ◽  
L. Perincheril ◽  
...  
Keyword(s):  

Author(s):  
Ramyanshu Datta ◽  
Robert Montoye ◽  
Kevin Nowka ◽  
Jun Sawada ◽  
Jacob A. Abraham
Keyword(s):  

1993 ◽  
Vol 03 (02) ◽  
pp. 269-292 ◽  
Author(s):  
MICHAEL PETER KENNEDY ◽  
CHAI WAH WU ◽  
STANLEY PAU ◽  
JAMES TOW

This paper is concerned with exploiting the architecture of a single-chip digital signal processor for integrating piecewise-linear ODEs. We show that DSPs can be usefully applied in the study of Chua's circuit family provided that one chooses a multistep integration algorithm which exploits their unique single-instruction multiply-and-accumulate feature.


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