Low Power Arithmetic Circuit Design for Multimedia Applications

The objective of this chapter is to describe the various designed arithmetic circuit for an application of multimedia circuit that can be used in a high-performance or mobile microprocessor with a particular set of optimisation criteria. The aim of this chapter is to describe the design method of binary arithmetic especially using by CMOS and Pass Transistor Logic technique. The pass transistor techniques are reduced the noise margin for small circuit, which can be explained in this chapter. This chapter further describe the types of arithmetic and its techniques. The technique design principle procedure should make the following decisions: circuit family (complementary static CMOS, pass-transistor, or Shannon Theorem based); type of arithmetic to be used. The decisions on the designed logic level significantly affect the propagation delay, area and power dissipation.

Signal-Adaptive Analog-to-Digital Converters for ULP Wearable and Implantable Medical Devices

The mission of this chapter is to introduce the reader the recent developments in the design of ultra-Low Power ADCs for Wearable and Implantable Medical Devices (WIMDs). The focus of this chapter will be on Signal-Adaptive Successive Approximation Register (SAR) ADC architectures and their derivatives, since the majority of the ULP medical devices rely on these architectures. The proposed chapter first provides an overview of the WIMDs, and electrophysiological signals. Then, basic SAR ADCs are introduced followed by the study of adaptive SAR ADCs. The chapter concludes with a brief summary of the other prevalent ADC architecture for WIMDs, namely the Level-Crossing ADCs.

State-of-the-Art Master Slave Flip-Flop Designs for Low Power VLSI Systems

This chapter presents a comprehensive overview of the conventional fully static master slave flip-flops used in low power VLSI systems where power budget is critical. In addition, the chapter also presents alternative realization of fully static master-slave flip-flops utilizing a modified feedback strategy. The flip-flops designed on the basis of modified architecture have been explained in detail and compared with state-of-the-art master slave flip-flop designs available in the literature. Extensive capacitance calculations have been performed in terms of clock load and capacitance at internal nodes has also been estimated for all the flip-flop configurations. This is executed in order to compare their relative power and delay characteristics which are well supported by simulation results.

Low Power Strategies for beyond Moore's Law Era

Semiconductor industries are facing a lot of problems in designing the chips consist of transistors with less than 10nm technology. Moore's law which predicted the scaling down of semiconductor devices has forced the researchers to look upon the devices in another aspect. So, various architectures and materials are invented to increase the reliability, speed and most importantly low power operation without increasing the size of devices. The on-set of nanotechnology and nano-science leads to unconventional 3D structure devices to and 0-dimensional structures. This chapter gives a general overview of the various technologies; materials and architectures researchers are concentrating to continue the technology beyond Moore's law with low power consumption.

Contemporary Low Power Design Approaches

This chapter describes three contemporary low power design approaches; a resistor-less bandgap reference circuit, a hybrid voltage level shifter with a diode connected NMOS and a modified dynamic comparator, each design with the objective to demonstrate the feasibility of contemporary approaches in achieving lower power VLSI design. All three designs are simulated in 0.18 µm CMOS technology using industrial simulation tool and the results are based on performance parameters defined in the chapter.

Case Study

Integrated circuits have been predominantly designed and developed by large firms and manufacturers; nowadays, any electronic engineer should be able to develop specific and innovative low-power designs using available open cores. This chapter presents the design process for a specific chip, beginning with a definition of its function, design considerations, power analysis, performance optimization, and chip optimization. The hardware and software for this circuit were developed for low-power implementation: it includes a processor, memory blocks, ports, buses, and a proposed application program, so it can be used as a starting point for other low-power very-large-scale integration (VLSI) circuits. The chip uses frequency synthesis and configuration parameters to deliver electric signals on a variety of waveforms and patterns. This design can be used in many research fields and application areas, where experiments or portable devices need low-power, programmable, and configurable electric signal generators.

The Design of Ultra Low Power RF CMOS LNA in Nanometer Technology

In this chapter, an ultra low power CMOS Common Gate LNA (CGLNA) with a Capacitive Cross-Coupled (CCC) gm boosting scheme is designed and analysed. The technique described has been employed in literature to reduce the Noise Figure (NF) and power dissipation. In this work we have extended the concept for low voltage operation along with improving NF and also for significant reduction in current consumption. A gm boosted CCC-CGLNA is implemented in 90nm CMOS technology. It has a gain of 9.9dB and a noise figure of 0.87dB at 2.4GHz ISM band and consumes less power (0.5mw) from 0.6V supply voltage. The designed gm boosted CCC-CGLNA is suitable for low power application in CMOS technologies.

Low Power VLSI Circuit Design using Energy Recovery Techniques

With the rapidly evolving silicon technology, the power density becomes increasingly high. Quadratically related to power, the voltage scaling offers a means of minimizing energy. However, power supply scaling demands less threshold voltage, which rises leakage current. Several low power techniques have been devised. This chapter deals with the non-conventional low power design solutions, based on adiabatic switching theory. In such circuits, the energy rather than getting dissipated during every cycle, is transferred back and forth between the logic and power-clock sources. A brief discussion on the reversible logic circuits will be presented followed by the fully adiabatic and quasi-adiabatic circuits. The use of power-clock sources for operating the adiabatic circuits will also be introduced. The generalized energetics of an adiabatic circuit followed by the typical loss models of the adiabatic families are presented. Some of the adiabatic circuits employing CMOS transistors are introduced in the chapter. A short comparison for the adiabatic circuit leakage models follows.

Challenges and Limitations of Low Power Techniques

In contemporary world the technology has kept its vast identity in developing ultra NANO devices to give up the compact device utilities, in VLSI, Metal Oxide Semiconductor device plays an key role in power dissipation product, in terms of MOS theory characteristics it is predefined that a MOS transistor can conduct easily with low voltage which gives low power but in DSM technology there is a likelihood to achieve ultra low power, so this can be achieved due to the rapid shrinking of gate length, here the chapter deals with challenges and limitations of low power techniques. The predominant way to generate low power is to start with the fundamental principles that are defined in the existing technologies that it gives low power with less leakage current. Apart from this parameter consideration is also required to achieve this. The successful and the major parameter in generating low power is that the shrinking of supply voltage. To go through this, upcoming sections gives the brief idea about the different techniques that are utilized to generate low power with less leakage.

Low Power Design of High Speed Communication System Using IO Standard Technique over 28 nm VLSI Chip

The low power design of Very Large Scale Integration (VLSI) system is one of the hot topic in research. In this chapter, the low power design for VLSI based high-speed communication is realized over 28 nm VLSI chip packed in UltraScale Field Programming Gate Array (FPGA) using proposed technique. The high-speed communication system is taken as case study for the low power design of VLSI system. Similarly, various VLSI design system can be realized to achieve the low power VLSI system design goal. High-speed communication systems provide the smooth operation for global internet traffic and requires high power devices and components.IO standard is powerful interface tool that provides low power consumption using the fast signal termination by mean of electrical characteristics. In result for this work, more than 96% power reduction is achieved for VLSI based high-speed communication system, when operated at 500 GHZ, 900 GHz, 10 THz and 17 THz carrier frequencies using the High-Speed Unterminated Logic IO Standard. The power analysis is performed using XPA analyzer in Xilinx suite.