Design of Non-volatile Capacitive Crossbar Array for In-Memory Computing

Author(s):  
Yuan-Chun Luo ◽  
Anni Lu ◽  
Jae Hur ◽  
Shaolan Li ◽  
Shimeng Yu
Keyword(s):  
2020 ◽  
Vol 59 (SM) ◽  
pp. SMMC03
Author(s):  
Mamoru Joko ◽  
Yusuke Hayashi ◽  
Tetsuya Tohei ◽  
Akira Sakai

2017 ◽  
Vol 46 (1) ◽  
pp. 122-137 ◽  
Author(s):  
Alexander Dozortsev ◽  
Israel Goldshtein ◽  
Shahar Kvatinsky
Keyword(s):  

2021 ◽  
pp. 2103376 ◽  
Author(s):  
Sifan Li ◽  
Mei‐Er Pam ◽  
Yesheng Li ◽  
Li Chen ◽  
Yu‐Chieh Chien ◽  
...  

2021 ◽  
Vol 118 (11) ◽  
pp. 112106
Author(s):  
Jinsu Jung ◽  
Dongjoo Bae ◽  
Sungho Kim ◽  
Hee-Dong Kim

2020 ◽  
Vol 117 (15) ◽  
pp. 152103 ◽  
Author(s):  
Tae-Hyeon Kim ◽  
Hussein Nili ◽  
Min-Hwi Kim ◽  
Kyung Kyu Min ◽  
Byung-Gook Park ◽  
...  

Electronics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 224 ◽  
Author(s):  
Zhensen Tang ◽  
Yao Wang ◽  
Yaqing Chi ◽  
Liang Fang

In this paper, the dependence of sensing currents on various device parameters is comprehensively studied by simulating the complete crossbar array rather than its equivalent analytical model. The worst-case scenario for read operation is strictly analyzed and defined in terms of selected location and data pattern, respectively, based on the effect of parasitic sneak paths and interconnection resistance. It is shown that the worst-case data pattern depends on the trade-off between the shunting effect of the parasitic sneak paths and the current injection effect of the parasitic sneak leakage, thus requiring specific analysis in practical simulations. In dealing with that, we propose a concept of the threshold array size incorporating the trade-off to define the parameter-dependent worst-case data pattern. This figure-of-merit provides guidelines for the worst-case scenario analysis of the crossbar array read operations.


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