A Controller Augmentation Method to Improve Transition Fault Coverage for RTL Data-Paths

2019 ◽  
Author(s):  
Yuki Takeuchi ◽  
Toshinori Hosokawa ◽  
Hiroshi Yamazaki ◽  
Masayoshi Yoshimura
Keyword(s):  
Fault Coverage ◽  
Transition Fault

scholarly journals On-chip Generation of Functional Tests with Reduced Delay and Power

2017 ◽  
Vol 6 (1) ◽  
pp. 36-46
Author(s):  
Hemanth Kumar Motamarri ◽  
B. Leela Kumari
Keyword(s):  
Test Generation ◽  
Fault Coverage ◽  
Pattern Generation ◽  
Functional Tests ◽  
Primary Input ◽  
Transition Fault ◽  
High Transition ◽  
On Chip

This paper describes different methods  on-chip test generation method for functional tests. The hardware was based on application of primary input sequences in order to allow the circuit to produce reachable states. Random primary input sequences were modeled to avoid repeated synchronization and thus yields varied sets of reachable states by implementing a decoder in between circuit and LFSR. The on-chip generation of functional tests require simple hardware and achieved high transition fault coverage for testable circuits. Further, power and delay can be reduced by using Bit Swapping LFSR (BS-LFSR). This technique yields less number of transitions for all pattern generation. Bit-swapping (BS) technique is less complex and more reliable to hardware miscommunications.

A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes

2010 ◽  
Vol 6 (2) ◽  
pp. 359-374 ◽  
Author(s):  
F. Wu ◽  
L. Dilillo ◽  
A. Bosio ◽  
P. Girard ◽  
S. Pravossoudovitch ◽  
...  
Keyword(s):  
Power Dissipation ◽  
Fault Coverage ◽  
Comprehensive Analysis ◽  
Test Power ◽  
Transition Fault
Sign in / Sign up

Export Citation Format

Share Document