scholarly journals On-chip Generation of Functional Tests with Reduced Delay and Power

2017 ◽  
Vol 6 (1) ◽  
pp. 36-46
Author(s):  
Hemanth Kumar Motamarri ◽  
B. Leela Kumari
Keyword(s):  
Test Generation ◽  
Fault Coverage ◽  
Pattern Generation ◽  
Functional Tests ◽  
Primary Input ◽  
Transition Fault ◽  
High Transition ◽  
On Chip

This paper describes different methods  on-chip test generation method for functional tests. The hardware was based on application of primary input sequences in order to allow the circuit to produce reachable states. Random primary input sequences were modeled to avoid repeated synchronization and thus yields varied sets of reachable states by implementing a decoder in between circuit and LFSR. The on-chip generation of functional tests require simple hardware and achieved high transition fault coverage for testable circuits. Further, power and delay can be reduced by using Bit Swapping LFSR (BS-LFSR). This technique yields less number of transitions for all pattern generation. Bit-swapping (BS) technique is less complex and more reliable to hardware miscommunications.

An On-Chip Clock Controller for Testing Fault in System on Chip

2013 ◽  
Vol 347-350 ◽  
pp. 724-728
Author(s):  
Wei Lin ◽  
Wen Long Shi
Keyword(s):  
Integrated Circuit ◽  
Test Pattern ◽  
Fault Coverage ◽  
System On Chip ◽  
Pattern Generation ◽  
Integrated Circuit Design ◽  
Scan Test ◽  
High Efficient ◽  
Transition Delay ◽  
On Chip

In this paper, an on-chip clock (OCC) controller with bypass function based on an internal phase locked loop (PLL) is designed to test the faults in system on chip (SOC), such as the transition-delay faults and the stuck-at faults. A clock chain logic which can eliminate the metastable state is realized to generate an enable signal for the OCC controller, and then, the test pattern is generated by the automatic test pattern generation (ATPG) tools. Next, the scan test pattern is simulated by the Synopsys tool and the correctness of the design is verified. The result shows that the design of at-speed scan test in this paper is high efficient for detecting the timing-related defects. Finally, the 89.29 percent transition-delay fault coverage and the 94.50 percent stuck-at fault coverage are achieved, and it is successfully applied to an integrated circuit design.

Equivalent Faults under Launch-on-Shift (LOS) Tests with Equal Primary Input Vectors

2021 ◽  
Vol 26 (4) ◽  
pp. 1-15
Author(s):  
Irith Pomeranz
Keyword(s):  
Test Generation ◽  
Fault Simulation ◽  
Single Cycle ◽  
Primary Input ◽  
Test Set ◽  
Efficient Procedure ◽  
Test Compaction ◽  
Transition Faults ◽  
Transition Fault ◽  
Types Of Faults

A recent work showed that it is possible to transform a single-cycle test for stuck-at faults into a launch-on-shift (LOS) test that is guaranteed to detect the same stuck-at faults without any logic or fault simulation. The LOS test also detects transition faults. This was used for obtaining a compact LOS test set that detects both types of faults. In the scenario where LOS tests are used for both stuck-at and transition faults, this article observes that, under certain conditions, the detection of a stuck-at fault guarantees the detection of a corresponding transition fault. This implies that the two faults are equivalent under LOS tests. Equivalence can be used for reducing the set of target faults for test generation and test compaction. The article develops this notion of equivalence under LOS tests with equal primary input vectors and provides an efficient procedure for identifying it. It presents experimental results to demonstrate that such equivalences exist in benchmark circuits, and shows an unexpected effect on a test compaction procedure.

An Enhanced Evolutionary Technique for the Generation of Compact Reconfigurable Scan-Network Tests

2019 ◽  
Vol 28 (supp01) ◽  
pp. 1940007 ◽  
Author(s):  
Riccardo Cantoro ◽  
Aleksa Damljanovic ◽  
Matteo Sonza Reorda ◽  
Giovanni Squillero
Keyword(s):  
Test Generation ◽  
Pattern Generation ◽  
Test Time ◽  
Automatic Test Pattern Generation ◽  
Permanent Faults ◽  
Evolutionary Technique ◽  
Standard Set ◽  
On Chip ◽  
Processing Techniques ◽  
And Control

Nowadays, many Integrated Systems embed auxiliary on-chip instruments whose function is to perform test, debug, calibration, configuration, etc. The growing complexity and the increasing number of these instruments have led to new solutions for their access and control, such as the IEEE 1687 standard. The standard introduces an infrastructure composed of scan chains incorporating configurable elements for accessing the instruments in a flexible manner. Such an infrastructure is known as Reconfigurable Scan Network or RSN. Since permanent faults affecting the circuitry can cause malfunction, i.e., inappropriate behavior, detecting them is of utmost importance. This paper addresses the issue of generating effective sequences for testing the reconfigurable elements within RSNs using evolutionary computation. Test configurations are extracted with automatic test pattern generation (ATPG) and used to guide the evolution. Post-processing techniques are proposed to improve the evolutionary fittest solution. Results on a standard set of benchmark networks show up to 27% reduced test time with respect to test generation based on RSN exploration.

Enabling Electro-Optical Failure Analysis within Extreme Compression Test Architecture

2016 ◽  
Author(s):  
Rudolf Schlangen ◽  
Jon Colburn ◽  
Joe Sarmiento ◽  
Bala Tarun Nelapatla ◽  
Puneet Gupta
Keyword(s):  
Failure Analysis ◽  
Compression Test ◽  
Test Pattern ◽  
Pattern Generation ◽  
Output Data ◽  
Test Compression ◽  
Test Loop ◽  
On Chip ◽  
Test Architecture

Abstract Driven by the need for higher test-compression, increasingly many chip-makers are adopting new DFT architectures such as “Extreme-Compression” (XTR, supported by Synopsys) with on-chip pattern generation and MISR based compression of chain output data. This paper discusses test-loop requirements in general and gives Advantest 93k specific guidelines on test-pattern release and ATE setup necessary to enable the most established EFA techniques such as LVP and SDL (aka DLS, LADA) within the XTR test architecture.

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