On achieving a complete fault coverage for sequential machines using the transition fault model

Author(s):  
Irith Pomeranz ◽  
Sudhakar M. Reddy
VLSI Design ◽  
1996 ◽  
Vol 4 (3) ◽  
pp. 231-242 ◽  
Author(s):  
Sankaran M. Menon ◽  
Yashwant K. Malaiya ◽  
Anura P. Jayasumana

Bipolar Emitter Coupled Logic (ECL) devices can now be fabricated at higher densities and consumes much lower power. Behaviour of simple and complex ECL gates are examined in the presence of physical faults. The effectiveness of the classical stuck-at model in representing physical failures in ECL gates is examined. It is shown that the conventional stuck-at fault model cannot represent a majority of circuit level faults. A new augmented stuck-at fault model is presented which provides a significantly higher coverage of physical failures. The model may be applicable to other logic families that use logic gates with both true and complementary outputs. A design for testability approach is suggested for on-line detection of certain error conditions occurring in gates with true and complementary outputs which is a normal implementation for ECL devices.


Author(s):  
Mahilchi Milir Vaseekar Kumar ◽  
Spyros Tragoudas ◽  
Sreejit Chakravarty ◽  
Rathish Jayabharathi

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