Noise figure of a 3-stage hybrid amplifier using parametric wavelength converters and EDFA

Author(s):  
Afshin Shamsshooli ◽  
Cheng Guo ◽  
Michael Vasilyev ◽  
Youichi Akasaka ◽  
Tadashi Ikeuchi
2021 ◽  
Author(s):  
Cheng Guo ◽  
Afshin Shamsshooli ◽  
Michael Vasilyev ◽  
Youichi Akasaka ◽  
Paparao Palacharla

Author(s):  
Cheng Guo ◽  
Afshin Shamsshooli ◽  
Youichi Akasaka ◽  
Tadashi Ikeuchi ◽  
Michael Vasilyev

2020 ◽  
Vol E103.C (7) ◽  
pp. 335-340
Author(s):  
Maizan MUHAMAD ◽  
Norhayati SOIN ◽  
Harikrishnan RAMIAH

Author(s):  
K. Pongot ◽  
J.S. Hamidon ◽  
A. Ahmad ◽  
M.K. Suaidi ◽  
A.H. Hamidon ◽  
...  
Keyword(s):  

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 804
Author(s):  
Gibeom Shin ◽  
Kyunghwan Kim ◽  
Kangseop Lee ◽  
Hyun-Hak Jeong ◽  
Ho-Jin Song

This paper presents a variable-gain amplifier (VGA) in the 68–78 GHz range. To reduce DC power consumption, the drain voltage was set to 0.5 V with competitive performance in the gain and the noise figure. High-Q shunt capacitors were employed at the gate terminal of the core transistors to move input matching points for easy matching with a compact transformer. The four stages amplifier fabricated in 40-nm bulk complementary metal oxide semiconductor (CMOS) showed a peak gain of 24.5 dB at 71.3 GHz and 3‑dB bandwidth of more than 10 GHz in 68–78 GHz range with approximately 4.8-mW power consumption per stage. Gate-bias control of the second stage in which feedback capacitances were neutralized with cross-coupled capacitors allowed us to vary the gain by around 21 dB in the operating frequency band. The noise figure was estimated to be better than 5.9 dB in the operating frequency band from the full electromagnetic (EM) simulation.


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