Deep learning algorithms are a key component of many state-of-the-art
vision systems, especially as Convolutional Neural Networks (CNN)
outperform most solutions in the sense of accuracy. To apply such
algorithms in real-time applications, one has to address the challenges
of memory and computational complexity. To deal with the first issue,
we use networks with reduced precision, specifically a binary neural
network (also known as XNOR). To satisfy the computational requirements,
we propose to use highly parallel and low-power FPGA devices. In this
work, we explore the possibility of accelerating XNOR networks for
traffic sign classification. The trained binary networks are implemented
on the ZCU 104 development board, equipped with a Zynq UltraScale+
MPSoC device using two different approaches. Firstly, we propose a
custom HDL accelerator for XNOR networks, which enables the inference
with almost 450 fps. Even better results are obtained with the second
method - the Xilinx FINN accelerator - enabling to process input images
with around 550 frame rate. Both approaches provide over 96% accuracy on
the test set.
Exploration of Hardware Acceleration Methods for an XNOR Traffic Signs Classifier