A High Speed Parallel Timing Recovery Algorithm and Its FPGA Implementation

2011 2nd International Symposium on Intelligence Information Processing and Trusted Computing ◽

10.1109/iptc.2011.23 ◽

2011 ◽

Author(s):

Changxing Lin ◽

Jian Zhang ◽

Beibei Shao

Keyword(s):

Fpga Implementation ◽

Timing Recovery ◽

Recovery Algorithm

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Low Complexity Timing Recovery Algorithm for PAM-8 in High Speed Direct Detection Short Range Links

Optical Fiber Communication Conference ◽

10.1364/ofc.2017.w2a.54 ◽

2017 ◽

Author(s):

Aditya Kakkar ◽

Jaime Rodrigo Navarro ◽

Xiaodan Pang ◽

Oskars Ozolins ◽

Richard Schatz ◽

...

Keyword(s):

Short Range ◽

Direct Detection ◽

Low Complexity ◽

Timing Recovery ◽

Recovery Algorithm

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Design, FPGA implementation and statistical analysis of a high-speed and low-area TRNG based on an AES s-box post-processing technique

ISA Transactions ◽

10.1016/j.isatra.2021.01.054 ◽

2021 ◽

Author(s):

Ali Murat Gari̇pcan ◽

Ebubekir Erdem

Keyword(s):

Statistical Analysis ◽

Processing Technique ◽

Fpga Implementation ◽

Post Processing ◽

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FPGA Implementation and Study of Synchronization of Modified Chua’s Circuit-Based Chaotic Oscillator for High-Speed Secure Communications

2020 IEEE 8th Workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE) ◽

10.1109/aieee51419.2021.9435783 ◽

2021 ◽

Author(s):

Filips Capligins ◽

Anna Litvinenko ◽

Arturs Aboltins ◽

Deniss Kolosovs

Keyword(s):

Fpga Implementation ◽

Chaotic Oscillator ◽

Secure Communications ◽

Chua’S Circuit ◽

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High-Speed and Scalable FPGA Implementation of the Key Generation for the Leighton-Micali Signature Protocol

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401177 ◽

2021 ◽

Author(s):

Yifeng Song ◽

Xiao Hu ◽

Wenhao Wang ◽

Jing Tian ◽

Zhongfeng Wang

Keyword(s):

Fpga Implementation ◽

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FPGA implementation of high speed Vedic multiplier

International Conference & Workshop on Electronics & Telecommunication Engineering (ICWET 2016) ◽

10.1049/cp.2016.1144 ◽

2016 ◽

Author(s):

S.N. Gadakh ◽

A.S. Khade

Keyword(s):

Fpga Implementation ◽

Vedic Multiplier

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AES-128 Cipher. High Speed, Low Cost FPGA Implementation

2007 3rd Southern Conference on Programmable Logic ◽

10.1109/spl.2007.371748 ◽

2007 ◽

Author(s):

Monica Liberatori ◽

Fernando Otero ◽

J. C. Bonadero ◽

Jorge Castineira

Keyword(s):

Low Cost ◽

Fpga Implementation

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FPGA Implementation of an Efficient High Speed Max-log-MAP Decoder

2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI) ◽

10.1109/icacci.2018.8554365 ◽

2018 ◽

Author(s):

Aishwarya Ambat ◽

Karthi Balasubramanian ◽

B. Yamuna ◽

Deepak Mishra

Keyword(s):

Fpga Implementation ◽

Map Decoder ◽

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High-speed parallel matched filter designing and FPGA implementation

Wuhan University Journal of Natural Sciences ◽

10.1007/s11859-010-0662-2 ◽

2010 ◽

Vol 15 (4) ◽

pp. 335-339

Author(s):

Qinglin Zhang ◽

Shuzhen Chen ◽

Yijun Luo ◽

Shan Wang

Keyword(s):

Matched Filter ◽

Fpga Implementation

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The FPGA Implementation of the High Speed Batchage Network

Advances in Intelligent Systems and Computing - Recent Developments in Mechatronics and Intelligent Robotics ◽

10.1007/978-3-030-00214-5_55 ◽

2018 ◽

pp. 434-440

Author(s):

Pu Wang ◽

Yuming Zhang ◽

Jun Yang

Keyword(s):

Fpga Implementation

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FPGA implementation of high speed 8-bit Vedic multiplier using barrel shifter

2013 International Conference on Energy Efficient Technologies for Sustainability ◽

10.1109/iceets.2013.6533349 ◽

2013 ◽

Author(s):

U. C. S. P. Kumar ◽

A. S. Goud ◽

A. Radhika

Keyword(s):

Fpga Implementation ◽

Vedic Multiplier ◽

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