Design, FPGA implementation and statistical analysis of a high-speed and low-area TRNG based on an AES s-box post-processing technique

2021 ◽  
Author(s):  
Ali Murat Gari̇pcan ◽  
Ebubekir Erdem
Keyword(s):  
Statistical Analysis ◽  
High Speed ◽  
Processing Technique ◽  
Fpga Implementation ◽  
Post Processing ◽  
Low Area

A Novel Generalized Approach for Real-Time Tool Condition Monitoring

2017 ◽  
Vol 140 (2) ◽  
Author(s):  
Mahmoud Hassan ◽  
Ahmad Sadek ◽  
M. H. Attia ◽  
Vincent Thomson
Keyword(s):  
Statistical Analysis ◽  
Condition Monitoring ◽  
High Speed ◽  
Threshold Level ◽  
Processing Technique ◽  
Spindle Motor ◽  
Tool Condition Monitoring ◽  
Important Principle ◽  
Tool Condition ◽  
Cutting Processes

In high-speed cutting processes, late replacement of defective tools may lead to machine breakdowns and badly affect the product quality, which subsequently lead to scrap parts and high process costs. Accurate tool condition detection is essential to achieve high level of competitiveness via increasing process productivity and standardizing the quality of the produced parts. Therefore, tool condition monitoring (TCM) systems have been widely emphasized as an important principle to achieve these industrial demands. Several studies for TCM were carried out to capture tool failure using complex conventional and artificial intelligence (AI) techniques. However, these studies suffer from the absence of standardization and generalization. Hence, this paper presents a robust and reliable processing technique for the cutting process signals to extract generalized features in time and frequency domains. The proposed technique masks the effects of the cutting conditions on the extracted features and accentuates the tool condition effect. Characterization and statistical analysis of the processed features were performed to examine their sensitivity to the tool condition. The results revealed the processing technique capability to separate the features extracted from the spindle motor current signals into two mutually exclusive clusters according to their tool condition. The statistical analysis results were employed to optimize the tool condition detection approach using linear discrimination analysis (LDA) model. The results indicate the capability of the processing technique to minimize the system learning effort and to detect tool wear above the threshold level with accuracy above 90%.

scholarly journals FPGA Implementation of High Speed Low Area DWT Based Invisible Image Watermarking Algorithm

2012 ◽  
Vol 30 ◽  
pp. 266-273 ◽  
Author(s):  
P Karthigaikumar ◽  
Anumol ◽  
K Baskaran
Keyword(s):  
High Speed ◽  
Image Watermarking ◽  
Fpga Implementation ◽  
Low Area

scholarly journals A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 2023
Author(s):  
Thanikodi Manoj Kumar ◽  
Kasarla Satish Reddy ◽  
Stefano Rinaldi ◽  
Bidare Divakarachari Parameshachari ◽  
Kavitha Arunachalam
Keyword(s):  
Data Security ◽  
High Speed ◽  
Fpga Implementation ◽  
Digital Data ◽  
Low Area ◽  
Aes Algorithm ◽  
Field Programmable ◽  
Hardware Architectures ◽  
Cyber Crimes ◽  
The Look

Nowadays, a huge amount of digital data is frequently changed among different embedded devices over wireless communication technologies. Data security is considered an important parameter for avoiding information loss and preventing cyber-crimes. This research article details the low power high-speed hardware architectures for the efficient field programmable gate array (FPGA) implementation of the advanced encryption standard (AES) algorithm to provide data security. This work does not depend on the look up tables (LUTs) for the implementation the SubBytes and InvSubBytes stages of transformations of the AES encryption and decryption; this new architecture uses combinational logical circuits for implementing SubBytes and InvSubBytes transformation. Due to the elimination of LUTs, unwanted delays are eliminated in this architecture and a subpipelining structure is introduced for improving the speed of the AES algorithm. Here, modified positive polarity reed muller (MPPRM) architecture is inserted to reduce the total hardware requirements, and comparisons are made with different implementations. With MPPRM architecture introduced in SubBytes stages, an efficient mixcolumn and invmixcolumn architecture that is suited to subpipelined round units is added. The performances of the proposed AES-MPPRM architecture is analyzed in terms of number of slice registers, flip flops, number of slice LUTs, number of logical elements, slices, bonded IOB, operating frequency and delay. There are five different AES architectures including LAES, AES-CTR, AES-CFA, AES-BSRD, and AES-EMCBE. The LUT of the AES-MPPRM architecture designed in the Spartan 6 is reduced up to 15.45% when compared to the AES-BSRD.

Experimental Investigation During Stall and Surge in a Transonic Fan Stage and Rotor-Only Configuration

2006 ◽  
Author(s):  
A. J. Gannon ◽  
G. V. Hobson ◽  
R. P. Shreeve ◽  
I. J. Villescas
Keyword(s):  
High Speed ◽  
Fast Response ◽  
Pressure Measurements ◽  
Post Processing ◽  
Transonic Compressor ◽  
Compressor Rotor ◽  
The Difference ◽  
Data Signal ◽  
Transonic Fan ◽  
Casing Pressure

High-speed pressure measurements of a transonic compressor rotor-stator stage and rotor-only configuration during stall and surge are presented. Rotational speed data showed the difference between the rotor-only case and rotor-stator stage. The rotor-only case stalled and remained stalled until the control throttle was opened. In the rotor-stator stage the compressor surged entering a cyclical stalling and then un-stalling pattern. An array of pressure probes was mounted in the case wall over the rotor for both configurations of the machine. The fast response probes were sampled at 196 608 Hz as the rotor was driven into stall. Inspection of the raw data signal allowed the size and speed of the stall cell during its growth to be investigated. Post-processing of the simultaneous signals of the casing pressure showed the development of the stall cell from the point of inception and allowed the structure of the stall cell to be viewed.

scholarly journals A post-processing technique for stabilizing the discontinuous pressure projection operator in marginally-resolved incompressible inviscid flow

2016 ◽  
Vol 139 ◽  
pp. 120-129 ◽  
Author(s):  
Sumedh M. Joshi ◽  
Peter J. Diamessis ◽  
Derek T. Steinmoeller ◽  
Marek Stastna ◽  
Greg N. Thomsen
Keyword(s):  
Projection Operator ◽  
Inviscid Flow ◽  
Processing Technique ◽  
Post Processing ◽  
Pressure Projection ◽  
Discontinuous Pressure
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