FPGA Implementation and Study of Synchronization of Modified Chua’s Circuit-Based Chaotic Oscillator for High-Speed Secure Communications

2021 ◽  
Author(s):  
Filips Capligins ◽  
Anna Litvinenko ◽  
Arturs Aboltins ◽  
Deniss Kolosovs
Keyword(s):  
High Speed ◽  
Fpga Implementation ◽  
Chaotic Oscillator ◽  
Secure Communications ◽  
Chua’S Circuit ◽  
Chua's Circuit

STABILITY OF OBSERVER-BASED CHAOTIC COMMUNICATIONS FOR A CLASS OF LUR'E SYSTEMS

2002 ◽  
Vol 12 (07) ◽  
pp. 1605-1618 ◽  
Author(s):  
JOSE ALVAREZ-RAMIREZ ◽  
HECTOR PUEBLA ◽  
ILSE CERVANTES
Keyword(s):  
Numerical Simulations ◽  
Chaotic Oscillator ◽  
Chua’S Circuit ◽  
Lur’E Systems ◽  
Chua's Circuit ◽  
Information Signal ◽  
Synchronization Signal ◽  
Chaotic Communications ◽  
The Stability

In this paper, the stability of observer-based chaotic communications using Lur'e systems is presented. In this approach, the transmitter contains a chaotic oscillator with an input that is modulate by the information signal. The receiver is composed by a copy of the transmitter driven by a synchronization signal. Some effects of transmission noise on the demodulation procedure are discussed. Numerical simulations on Chua's circuit are provided to illustrate our findings.

A NEW SYNCHRONIZATION PRINCIPLE FOR A CLASS OF LUR'E SYSTEMS WITH APPLICATIONS IN SECURE COMMUNICATION

2004 ◽  
Vol 14 (07) ◽  
pp. 2477-2491 ◽  
Author(s):  
SAMUEL BOWONG ◽  
F. M. MOUKAM KAKMENI ◽  
RODOUMTA KOINA
Keyword(s):  
Dynamical Systems ◽  
Secure Communication ◽  
Chaotic Oscillator ◽  
Secure Communications ◽  
Lur’E Systems ◽  
Synchronization Time ◽  
Chua's Circuit ◽  
Scalar Output ◽  
Information Signal ◽  
Synchronization Signal

In this Letter, we propose a new synchronization principle for a class of Lur'e systems. We design, using only a single scalar output, a possible class of observers to detect whether two dynamical systems exhibit identical oscillations. The proposed method is then applied to suggest a means to secure communications. The transmitter contains a chaotic oscillator with an input that is modulated by the information signal. The receiver is a copy of the transmitter driven by a synchronization signal. The advantage of this method over the existing one is that the synchronization time is explicitly computed. An illustrative example of the cubic Chua's circuit is given to show the effectiveness of the proposed approach.

scholarly journals Localization of Hidden Attractors in Chua’s System With Absolute Nonlinearity and Its FPGA Implementation

2021 ◽  
Vol 9 ◽  
Author(s):  
Xianming Wu ◽  
Huihai Wang ◽  
Shaobo He
Keyword(s):  
Basin Of Attraction ◽  
Digital Circuit ◽  
Fpga Implementation ◽  
Chaotic Attractors ◽  
Chua’S Circuit ◽  
Hidden Attractor ◽  
Hidden Attractors ◽  
Chua's Circuit ◽  
The Mathematical Model ◽  
The Basin Of Attraction

Investigation of the classical self-excited and hidden attractors in the modified Chua’s circuit is a hot and interesting topic. In this article, a novel Chua’s circuit system with an absolute item is investigated. According to the mathematical model, dynamic characteristics are analyzed, including symmetry, equilibrium stability analysis, Hopf bifurcation analysis, Lyapunov exponents, bifurcation diagram, and the basin of attraction. The hidden attractors are located theoretically. Then, the coexistence of the hidden limit cycle and self-excited chaotic attractors are observed numerically and experimentally. The numerical simulation results are consistent with the FPGA implementation results. It shows that the hidden attractor can be localized in the digital circuit.

Realization of Chaotic Circuits Using Lambda Diode

2017 ◽  
Vol 26 (12) ◽  
pp. 1750189 ◽  
Author(s):  
Bibha Kumari ◽  
Nisha Gupta
Keyword(s):  
Chaotic Behavior ◽  
Negative Resistance ◽  
Chaotic Oscillator ◽  
Chua’S Circuit ◽  
Linear Element ◽  
Chaotic Circuit ◽  
Poincaré Plot ◽  
Chua's Circuit ◽  
Nonlinear Resistor ◽  
Wide Range

This paper presents the design of novel autonomous and non-autonomous inductorless chaotic circuit using lambda diode. The autonomous chaotic circuit is implemented using Chua’s circuit, where the piece-wise linear element of Chua’s circuit called Chua’s diode is replaced by lambda diode. The lambda diode used as a nonlinear resistor in Chua’s circuit comprises of BJT, FET and resistors. The non-autonomous chaotic circuit is studied by replacing the piece-wise linear element of Murali–Lakshmana–Chua (MLC) circuit by lambda diode. The reason for employing lambda diode is that it has a wide range of negative resistance characteristics, which enable the circuit to operate at higher frequency ranges. The resulting chaotic oscillator can easily be made to operate at both low and high frequencies. The chaotic behavior of the circuit is established through Multisim simulations in the time and frequency domains. Both theoretical analysis and electronic circuit experiments are presented. The circuit’s chaotic characteristics are further confirmed by means of Poincare plot and the Bifurcation diagram. The observed route to chaos is period-adding.

CONTROLLING CHAOS IN A CHUA'S CIRCUIT USING NOTCH FILTERS

2009 ◽  
Vol 18 (06) ◽  
pp. 1137-1153 ◽  
Author(s):  
ASHRAF A. ZAHER ◽  
ABDULNASSER ABU-REZQ
Keyword(s):  
Power Spectrum ◽  
Period Doubling ◽  
Original System ◽  
Point Of View ◽  
Practical Implementation ◽  
Secure Communications ◽  
Chua’S Circuit ◽  
Notch Filters ◽  
Chua's Circuit ◽  
Processing Point

This paper explores the use of notch filters for the purpose of damping out chaotic oscillations. The design of the filter and the way it is interfaced to the system are investigated from a signal-processing point of view. A Chua's circuit, that has typical applications in synchronization and secure communications, is used to exemplify the suggested methodology where both theoretical and experimental results are provided. The power spectrum of the original system is analyzed to selectively damp-out portions of the power spectrum, thus truncating period-doubling, the original cause of chaos. Both single and double notch filters are explored to examine their effect on the performance of the modified system. Steady state analysis as well as issues regarding practical implementation are addressed and advantages and limitations of the proposed method are highlighted.

EXPERIMENTAL DEMONSTRATION OF SECURE COMMUNICATIONS VIA CHAOTIC SYNCHRONIZATION

1992 ◽  
Vol 02 (03) ◽  
pp. 709-713 ◽  
Author(s):  
Lj. KOCAREV ◽  
K. S. HALLE ◽  
K. ECKERT ◽  
L. O. CHUA ◽  
U. PARLITZ
Keyword(s):  
Recovery Process ◽  
Chaotic Signal ◽  
Chaotic Synchronization ◽  
Secure Communications ◽  
Chua’S Circuit ◽  
Experimental Demonstration ◽  
Chua's Circuit

Secure communications via chaotic synchronization is experimentally demonstrated using Chua's circuit. In our experiment the energy lost in the information-bearing signal is approximately 0.6 dBV. The reduction in chaotic signal after the recovery process is between -40 and -50 dBV.

scholarly journals Efficient design of chaos based 4 bit true random number generator on FPGA

2018 ◽  
Vol 7 (3) ◽  
pp. 1783
Author(s):  
Ramji Gupta ◽  
Alpana Pandey ◽  
R. K.Baghel
Keyword(s):  
Secure Communication ◽  
High Speed ◽  
Random Number ◽  
Random Number Generator ◽  
Fpga Implementation ◽  
Experimental Result ◽  
Chaotic Oscillator ◽  
Number Generator ◽  
Efficient Design ◽  
True Random Number Generator

True random number generator is a basic building block of any modern secure communication and cryptography system. FPGA implementation of any system has a flexible architecture and low-cost test cycle. In this paper, we present an FPGA implementation of a high speed true random number generator based on chaos oscillator which gives optimize ratio of bit rate to area. The proposed generator is faster and more compact than the existing chaotic oscillator based TRNGs. The Experimental result shows that the proposed TRNG gives 1439 Mbps with optimizing the use of LUTs and registers. It is verified that the generator passes all the NIST SP 800-22 tests. The proposed TRNG is implemented in two FPGA families Nexus 4 (Artix 7) DDR XC7A100TCSG-1 and Basys 3 XC7A35T1CPG236C (Artix 7) using Xilinx Vivado v.2017.3 design suite. 

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