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High-Speed and Scalable FPGA Implementation of the Key Generation for the Leighton-Micali Signature Protocol
2021 IEEE International Symposium on Circuits and Systems (ISCAS)
◽
10.1109/iscas51556.2021.9401177
◽
2021
◽
Author(s):
Yifeng Song
◽
Xiao Hu
◽
Wenhao Wang
◽
Jing Tian
◽
Zhongfeng Wang
Keyword(s):
High Speed
◽
Fpga Implementation
◽
Key Generation
Download Full-text
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References
Design, FPGA implementation and statistical analysis of a high-speed and low-area TRNG based on an AES s-box post-processing technique
ISA Transactions
◽
10.1016/j.isatra.2021.01.054
◽
2021
◽
Author(s):
Ali Murat Gari̇pcan
◽
Ebubekir Erdem
Keyword(s):
Statistical Analysis
◽
High Speed
◽
Processing Technique
◽
Fpga Implementation
◽
Post Processing
◽
Low Area
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A Low Area FPGA Implementation of Reversible Gate Encryption with Heterogeneous Key Generation
Circuits Systems and Signal Processing
◽
10.1007/s00034-021-01649-1
◽
2021
◽
Author(s):
K. Saranya
◽
K. N. Vijeyakumar
Keyword(s):
Fpga Implementation
◽
Key Generation
◽
Low Area
◽
Reversible Gate
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FPGA Implementation and Study of Synchronization of Modified Chua’s Circuit-Based Chaotic Oscillator for High-Speed Secure Communications
2020 IEEE 8th Workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE)
◽
10.1109/aieee51419.2021.9435783
◽
2021
◽
Author(s):
Filips Capligins
◽
Anna Litvinenko
◽
Arturs Aboltins
◽
Deniss Kolosovs
Keyword(s):
High Speed
◽
Fpga Implementation
◽
Chaotic Oscillator
◽
Secure Communications
◽
Chua’S Circuit
◽
Chua's Circuit
Download Full-text
FPGA implementation of high speed Vedic multiplier
International Conference & Workshop on Electronics & Telecommunication Engineering (ICWET 2016)
◽
10.1049/cp.2016.1144
◽
2016
◽
Cited By ~ 2
Author(s):
S.N. Gadakh
◽
A.S. Khade
Keyword(s):
High Speed
◽
Fpga Implementation
◽
Vedic Multiplier
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AES-128 Cipher. High Speed, Low Cost FPGA Implementation
2007 3rd Southern Conference on Programmable Logic
◽
10.1109/spl.2007.371748
◽
2007
◽
Cited By ~ 16
Author(s):
Monica Liberatori
◽
Fernando Otero
◽
J. C. Bonadero
◽
Jorge Castineira
Keyword(s):
High Speed
◽
Low Cost
◽
Fpga Implementation
Download Full-text
FPGA Implementation of an Efficient High Speed Max-log-MAP Decoder
2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI)
◽
10.1109/icacci.2018.8554365
◽
2018
◽
Cited By ~ 1
Author(s):
Aishwarya Ambat
◽
Karthi Balasubramanian
◽
B. Yamuna
◽
Deepak Mishra
Keyword(s):
High Speed
◽
Fpga Implementation
◽
Map Decoder
◽
Log Map
Download Full-text
High-speed parallel matched filter designing and FPGA implementation
Wuhan University Journal of Natural Sciences
◽
10.1007/s11859-010-0662-2
◽
2010
◽
Vol 15
(4)
◽
pp. 335-339
Author(s):
Qinglin Zhang
◽
Shuzhen Chen
◽
Yijun Luo
◽
Shan Wang
Keyword(s):
High Speed
◽
Matched Filter
◽
Fpga Implementation
Download Full-text
The FPGA Implementation of the High Speed Batchage Network
Advances in Intelligent Systems and Computing - Recent Developments in Mechatronics and Intelligent Robotics
◽
10.1007/978-3-030-00214-5_55
◽
2018
◽
pp. 434-440
Author(s):
Pu Wang
◽
Yuming Zhang
◽
Jun Yang
Keyword(s):
High Speed
◽
Fpga Implementation
Download Full-text
FPGA implementation of high speed 8-bit Vedic multiplier using barrel shifter
2013 International Conference on Energy Efficient Technologies for Sustainability
◽
10.1109/iceets.2013.6533349
◽
2013
◽
Cited By ~ 11
Author(s):
U. C. S. P. Kumar
◽
A. S. Goud
◽
A. Radhika
Keyword(s):
High Speed
◽
Fpga Implementation
◽
Vedic Multiplier
◽
Barrel Shifter
Download Full-text
High speed FPGA implementation of RSA encryption algorithm
10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003
◽
10.1109/icecs.2003.1302012
◽
2004
◽
Cited By ~ 3
Author(s):
O. Nibouche
◽
M. Nibouche
◽
A. Bouridane
Keyword(s):
High Speed
◽
Fpga Implementation
◽
Encryption Algorithm
Download Full-text
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