High speed low power architecture for memory management in a Viterbi decoder

1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96 ◽

10.1109/iscas.1996.541957 ◽

2002 ◽

Author(s):

E. Boutillon ◽

N. Demassieux

Keyword(s):

Low Power ◽

Memory Management ◽

Viterbi Decoder ◽

Power Architecture

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A high-speed low-power pipelined Viterbi Decoder: breaking the ACS-bottleneck

The 2010 International Conference on Green Circuits and Systems ◽

10.1109/icgcs.2010.5543044 ◽

2010 ◽

Author(s):

Kelvin Yi-Tse Lai

Keyword(s):

Low Power ◽

Viterbi Decoder

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A high-speed/low-power architecture for 1D discrete biorthogonal wavelet transform

2003 46th Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.2003.1562569 ◽

2006 ◽

Author(s):

I.S. Uzun ◽

A. Amira ◽

A. Bouridane

Keyword(s):

Wavelet Transform ◽

Low Power ◽

Biorthogonal Wavelet ◽

Biorthogonal Wavelet Transform ◽

Power Architecture

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VLSI implementation of a high-speed and low-power punctured Viterbi decoder

2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering. TENCOM '02. Proceedings. ◽

10.1109/tencon.2002.1180342 ◽

2003 ◽

Author(s):

Li Qiao ◽

You Yuxin ◽

Wang Jinxiang ◽

Ye Yizheng

Keyword(s):

Low Power ◽

Vlsi Implementation ◽

Viterbi Decoder

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High Speed Low-Power Viterbi Decoder Using Trellis Code Modulation

International Journal of Computing Algorithm ◽

10.20894/ijcoa.101.005.001.013 ◽

2016 ◽

Vol 5 (1) ◽

pp. 55-58

Author(s):

K. Neelaveni ◽

◽

G. Saravanakumar ◽

Keyword(s):

Low Power ◽

Viterbi Decoder ◽

Trellis Code ◽

Code Modulation

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An efficient metric normalization architecture for high-speed low-power viterbi decoder

TENCON 2007 - 2007 IEEE Region 10 Conference ◽

10.1109/tencon.2007.4429152 ◽

2007 ◽

Author(s):

Kelvin Yi-Tse Lai

Keyword(s):

Low Power ◽

Viterbi Decoder

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High-Speed Low-Power Viterbi Decoder Design for TCM Decoders

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2011.2111392 ◽

2012 ◽

Vol 20 (4) ◽

pp. 755-759 ◽

Author(s):

Jinjin He ◽

Huaping Liu ◽

Zhongfeng Wang ◽

Xinming Huang ◽

Kai Zhang

Keyword(s):

Low Power ◽

Viterbi Decoder ◽

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The Design of High-Speed and Low Power Consumption Bidirection Viterbi Decoder

2006 International Conference on Machine Learning and Cybernetics ◽

10.1109/icmlc.2006.258740 ◽

2006 ◽

Author(s):

Song Li ◽

Qing-ming Yi

Keyword(s):

Power Consumption ◽

Low Power ◽

Low Power Consumption ◽

Viterbi Decoder

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High-speed and high-coding-gain Viterbi decoder with low power consumption employing SST (scarce state transition) scheme

Electronics Letters ◽

10.1049/el:19860334 ◽

1986 ◽

Vol 22 (9) ◽

pp. 491 ◽

Author(s):

S. Kubota ◽

K. Ohtani ◽

S. Kato

Keyword(s):

Power Consumption ◽

Low Power ◽

State Transition ◽

Low Power Consumption ◽

Viterbi Decoder ◽

Coding Gain ◽

Transition Scheme

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A Three-Level Parallel High-Speed Low-Power Architecture for EBCOT of JPEG 2000

IEEE Transactions on Circuits and Systems for Video Technology ◽

10.1109/tcsvt.2006.881864 ◽

2006 ◽

Vol 16 (9) ◽

pp. 1153-1163 ◽

Author(s):

Y. Li ◽

M. Bayoumi

Keyword(s):

Low Power ◽

Jpeg 2000 ◽

Power Architecture

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A New Low-Power and High Speed Viterbi Decoder Architecture

Ubiquitous Convergence Technology - Lecture Notes in Computer Science ◽

10.1007/978-3-540-71789-8_29 ◽

2007 ◽

pp. 283-291

Author(s):

Chang-Jin Choi ◽

Sang-Hun Yoon ◽

Jong-Wha Chong ◽

Shouyin Lin

Keyword(s):

Low Power ◽

Viterbi Decoder ◽

Decoder Architecture

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