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High-Speed Low-Power Viterbi Decoder Design for TCM Decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
◽
10.1109/tvlsi.2011.2111392
◽
2012
◽
Vol 20
(4)
◽
pp. 755-759
◽
Cited By ~ 23
Author(s):
Jinjin He
◽
Huaping Liu
◽
Zhongfeng Wang
◽
Xinming Huang
◽
Kai Zhang
Keyword(s):
Low Power
◽
High Speed
◽
Viterbi Decoder
◽
Decoder Design
Download Full-text
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References
A high-speed low-power pipelined Viterbi Decoder: breaking the ACS-bottleneck
The 2010 International Conference on Green Circuits and Systems
◽
10.1109/icgcs.2010.5543044
◽
2010
◽
Cited By ~ 7
Author(s):
Kelvin Yi-Tse Lai
Keyword(s):
Low Power
◽
High Speed
◽
Viterbi Decoder
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A Low Power VITERBI Decoder Design With Minimum Transition Hybrid Register Exchange Processing For Wireless Applications
International Journal of VLSI Design & Communication Systems
◽
10.5121/vlsic.2010.1402
◽
2010
◽
Vol 1
(4)
◽
pp. 14-22
◽
Cited By ~ 1
Author(s):
S.L Haridas
◽
N.K Choudhari
Keyword(s):
Low Power
◽
Viterbi Decoder
◽
Wireless Applications
◽
Decoder Design
Download Full-text
VLSI implementation of a high-speed and low-power punctured Viterbi decoder
2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering. TENCOM '02. Proceedings.
◽
10.1109/tencon.2002.1180342
◽
2003
◽
Author(s):
Li Qiao
◽
You Yuxin
◽
Wang Jinxiang
◽
Ye Yizheng
Keyword(s):
Low Power
◽
High Speed
◽
Vlsi Implementation
◽
Viterbi Decoder
Download Full-text
High Speed Low-Power Viterbi Decoder Using Trellis Code Modulation
International Journal of Computing Algorithm
◽
10.20894/ijcoa.101.005.001.013
◽
2016
◽
Vol 5
(1)
◽
pp. 55-58
Author(s):
K. Neelaveni
◽
◽
G. Saravanakumar
◽
Keyword(s):
Low Power
◽
High Speed
◽
Viterbi Decoder
◽
Trellis Code
◽
Code Modulation
Download Full-text
An efficient metric normalization architecture for high-speed low-power viterbi decoder
TENCON 2007 - 2007 IEEE Region 10 Conference
◽
10.1109/tencon.2007.4429152
◽
2007
◽
Cited By ~ 2
Author(s):
Kelvin Yi-Tse Lai
Keyword(s):
Low Power
◽
High Speed
◽
Viterbi Decoder
Download Full-text
The Design of High-Speed and Low Power Consumption Bidirection Viterbi Decoder
2006 International Conference on Machine Learning and Cybernetics
◽
10.1109/icmlc.2006.258740
◽
2006
◽
Cited By ~ 2
Author(s):
Song Li
◽
Qing-ming Yi
Keyword(s):
Power Consumption
◽
Low Power
◽
High Speed
◽
Low Power Consumption
◽
Viterbi Decoder
Download Full-text
High-speed and high-coding-gain Viterbi decoder with low power consumption employing SST (scarce state transition) scheme
Electronics Letters
◽
10.1049/el:19860334
◽
1986
◽
Vol 22
(9)
◽
pp. 491
◽
Cited By ~ 19
Author(s):
S. Kubota
◽
K. Ohtani
◽
S. Kato
Keyword(s):
Power Consumption
◽
Low Power
◽
High Speed
◽
State Transition
◽
Low Power Consumption
◽
Viterbi Decoder
◽
Coding Gain
◽
Transition Scheme
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High speed low power architecture for memory management in a Viterbi decoder
1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96
◽
10.1109/iscas.1996.541957
◽
2002
◽
Cited By ~ 5
Author(s):
E. Boutillon
◽
N. Demassieux
Keyword(s):
Low Power
◽
Memory Management
◽
High Speed
◽
Viterbi Decoder
◽
Power Architecture
Download Full-text
Low power Viterbi decoder design based on reversible logic gates
2017 4th International Conference on Electronics and Communication Systems (ICECS)
◽
10.1109/ecs.2017.8067869
◽
2017
◽
Author(s):
K B Naveen
◽
G S Puneeth
◽
M N Sree Rangaraju
Keyword(s):
Low Power
◽
Logic Gates
◽
Reversible Logic
◽
Viterbi Decoder
◽
Decoder Design
◽
Reversible Logic Gates
Download Full-text
An Efficient Low Power Viterbi Decoder Design using T-algorithm
International Journal of Computer Applications
◽
10.5120/13246-0707
◽
2013
◽
Vol 76
(5)
◽
pp. 34-39
Author(s):
K. SridharReddy
◽
M. Nagarjuna
◽
H. Shravan Kumar
Keyword(s):
Low Power
◽
Viterbi Decoder
◽
Decoder Design
Download Full-text
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