High-performance multiplexer-based logic synthesis using pass-transistor logic

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353) ◽

10.1109/iscas.2000.856327 ◽

2002 ◽

Author(s):

Shen-Fu Hsiao ◽

Jia-Siang Yeh ◽

Da-Yen Chen

Keyword(s):

High Performance ◽

Logic Synthesis ◽

Pass Transistor ◽

Pass Transistor Logic

High-performance Multiplexer-based Logic Synthesis Using Pass-transistor Logic

VLSI Design ◽

10.1080/1065514021000054736 ◽

2002 ◽

Vol 15 (1) ◽

pp. 417-426 ◽

Cited By ~ 6

Author(s):

Shen-Fu Hsiao ◽

Jia-Siang Yeh ◽

Da-Yen Chen

Keyword(s):

Boolean Functions ◽

High Performance ◽

Voltage Drop ◽

Critical Path ◽

Logic Synthesis ◽

Path Delay ◽

Minimum Width ◽

Pass Transistor ◽

Pass Transistor Logic ◽

Function Sharing

An automatic logic/circuit synthesizer is developed which takes several Boolean functions as input and generates netlist output with basic composing cells from the pass-transistor cell library containing only two types of cells: 2-to-1 multiplexers and inverters. The synthesis procedure first constructs efficient binary decision diagrams (BDDs) for these Boolean functions considering both multi-function sharing and minimum width. Each node in the BDD trees is realized by using a 2-to-1 multiplexer (MUX) of proper driving capability designed pass-transistor logic. The inverters are then inserted all along the MUX paths in order to improve the speed performance and to alleviate the voltage-drop problem. Several methods are proposed to reduce the critical path delay in the multiplexer-chains for generation of faster circuits. Compared to the recently proposed pass-transistor-based top-down design, our synthesizer has better speed and area performance due to the reduced number of cascaded inverters.

A fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic

Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273) ◽

10.1109/iccd.1998.727062 ◽

2002 ◽

Author(s):

Yanbin Jiang ◽

S.S. Sapatnekar ◽

C. Bamji

Keyword(s):

High Performance ◽

Pass Transistor ◽

Pass Transistor Logic

Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits

APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems ◽

10.1109/apccas.2006.342077 ◽

2006 ◽

Author(s):

Shen-Fu Hsiao ◽

Ming-Yu Tsai ◽

Chia-Sheng Wen

Keyword(s):

Logic Synthesis ◽

Sequential Circuits ◽

Pass Transistor ◽

Pass Transistor Logic ◽

Efficient Pass

Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction

2008 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2008.4541844 ◽

2008 ◽

Author(s):

Shen-Fu Hsiao ◽

Ming-Yu Tsai ◽

Chia-Sheng Wen

Keyword(s):

Logic Synthesis ◽

Pass Transistor ◽

Pass Transistor Logic

Performance Analysis of Reversed Binary Decision Diagram Pass Transistor Logic Synthesis

International Journal of Circuit Theory and Applications ◽

10.1002/cta.822 ◽

2011 ◽

Vol 41 (8) ◽

pp. 844-853 ◽

Cited By ~ 2

Author(s):

Thangavel Bhuvaneswari ◽

Vishnuvajjula Prasad ◽

Ajay Kumar Singh ◽

Chinnaiyan Senthilpari

Keyword(s):

Performance Analysis ◽

Logic Synthesis ◽

Binary Decision Diagram ◽

Binary Decision ◽

Pass Transistor ◽

Pass Transistor Logic

High Performance CMOS 2-input NAND Based on Low-race Split-level Charge-recycling Pass-transistor Logic

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools ◽

10.1109/dsd.2009.181 ◽

2009 ◽

Author(s):

José Carlos Garcia-Montesdeoca ◽

Juan A. Montiel-Nelson ◽

Saeid Nooshabadi

Keyword(s):

High Performance ◽

Charge Recycling ◽

Pass Transistor ◽

Pass Transistor Logic

Technology mapping for high-performance static CMOS and pass transistor logic designs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/92.953492 ◽

2001 ◽

Vol 9 (5) ◽

pp. 577-589 ◽

Cited By ~ 9

Author(s):

Yanbin Jiang ◽

S.S. Sapatnekar ◽

C. Bamji

Keyword(s):

High Performance ◽

Technology Mapping ◽

Pass Transistor ◽

Pass Transistor Logic

High performance Complementary Pass transistor Logic full adder

Proceedings of 2011 International Conference on Electronic & Mechanical Engineering and Information Technology ◽

10.1109/emeit.2011.6023114 ◽

2011 ◽

Cited By ~ 1

Author(s):

Lixin Gao

Keyword(s):

High Performance ◽

Full Adder ◽

Pass Transistor ◽

Pass Transistor Logic

An efficient algorithm for low power pass transistor logic synthesis

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design ◽

10.1109/aspdac.2002.994890 ◽

2003 ◽

Cited By ~ 4

Author(s):

R.S. Shelar ◽

S.S. Sapatnekar

Keyword(s):

Low Power ◽

Efficient Algorithm ◽

Logic Synthesis ◽

Pass Transistor ◽

Pass Transistor Logic

Reversed signal propagation BDD based low-power pass-transistor logic synthesis

IEEJ Transactions on Electrical and Electronic Engineering ◽

10.1002/tee.21920 ◽

2013 ◽

Vol 8 (S1) ◽

pp. S66-S71

Author(s):

Thangavel Bhuvaneswari ◽

Vishnuvajjula Charan Prasad ◽

Ajay Kumar Singh

Keyword(s):

Low Power ◽

Logic Synthesis ◽

Signal Propagation ◽

Pass Transistor ◽

Pass Transistor Logic