Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design
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Efficient approximate balanced truncation of general large-scale RLC systems via Krylov methods

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design ◽

10.1109/aspdac.2002.994940 ◽

2005 ◽

Author(s):

Q. Su ◽

V. Balakrishnan ◽

C.-K. Koh

Keyword(s):

Large Scale ◽

Balanced Truncation ◽

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Architecture and design of a high performance SRAM for SOC design

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design ◽

10.1109/aspdac.2002.994961 ◽

2003 ◽

Author(s):

S. Singh ◽

S. Azmi ◽

N. Agrawal ◽

P. Phani ◽

A. Rout

Keyword(s):

High Performance ◽

Architecture And Design

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Interconnect energy dissipation in high-speed ULSI circuits

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design ◽

10.1109/aspdac.2002.994900 ◽

2003 ◽

Author(s):

P. Heydari ◽

M. Pedram

Keyword(s):

Energy Dissipation ◽

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Compiler-directed array interleaving for reducing energy in multi-bank memories

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design ◽

10.1109/aspdac.2002.994936 ◽

2003 ◽

Author(s):

V. Delaluz ◽

M. Kandemir ◽

N. Vijaykrishnan ◽

M.J. Irwin ◽

A. Sivasubramaniam ◽

...

Keyword(s):

Reducing Energy

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Trends and challenges in VLSI technology scaling towards 100 nm

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design ◽

10.1109/aspdac.2002.994875 ◽

2003 ◽

Author(s):

S. Rusu ◽

M. Sachdev ◽

C. Svensson ◽

B. Nauta

Keyword(s):

Technology Scaling ◽

Vlsi Technology

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Development of ASIC chip-set for high-end network processing application a case study

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design ◽

10.1109/aspdac.2002.995029 ◽

2003 ◽

Author(s):

S. Patel

Keyword(s):

Processing Application ◽

Asic Chip ◽

Network Processing

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VLSI implementation of 2-D DWT/IDWT cores using 9/7-tap filter banks based on the non-expansive symmetric extension scheme

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design ◽

10.1109/aspdac.2002.994959 ◽

2003 ◽

Author(s):

K. Seth ◽

S. Srinivasan

Keyword(s):

Filter Banks ◽

Vlsi Implementation ◽

Symmetric Extension

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An adaptive interconnect-length driven placer

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design ◽

10.1109/aspdac.2002.994953 ◽

2003 ◽

Author(s):

Chi-Ming Tsai ◽

Kun-Tien Kuo ◽

Chyi-Hui Hong ◽

Rung-Bin Lin

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Automatic model refinement for fast architecture exploration [SoC design]

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design ◽

10.1109/aspdac.2002.994944 ◽

2003 ◽

Author(s):

J. Peng ◽

S. Abdi ◽

D. Gajski

Keyword(s):

Model Refinement ◽

Architecture Exploration

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Divide-and-conquer IDDQ testing for core-based system chips

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design ◽

10.1109/aspdac.2002.995025 ◽

2003 ◽

Author(s):

C.P. Ravikumar ◽

R. Kumar

Keyword(s):

Divide And Conquer ◽

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