Performance Analysis of Reversed Binary Decision Diagram Pass Transistor Logic Synthesis

Thangavel Bhuvaneswari; Vishnuvajjula Prasad; Ajay Kumar Singh; Chinnaiyan Senthilpari

doi:10.1002/cta.822

Performance Analysis of Reversed Binary Decision Diagram Pass Transistor Logic Synthesis

International Journal of Circuit Theory and Applications ◽

10.1002/cta.822 ◽

2011 ◽

Vol 41 (8) ◽

pp. 844-853 ◽

Cited By ~ 2

Author(s):

Thangavel Bhuvaneswari ◽

Vishnuvajjula Prasad ◽

Ajay Kumar Singh ◽

Chinnaiyan Senthilpari

Keyword(s):

Performance Analysis ◽

Logic Synthesis ◽

Binary Decision Diagram ◽

Binary Decision ◽

Pass Transistor ◽

Pass Transistor Logic

Synthesize pass transistor logic gate by using free binary decision diagram

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) ◽

10.1109/asic.1997.617005 ◽

2002 ◽

Cited By ~ 3

Author(s):

M. Tachibana

Keyword(s):

Logic Gate ◽

Binary Decision Diagram ◽

Binary Decision ◽

Pass Transistor ◽

Pass Transistor Logic

High-performance multiplexer-based logic synthesis using pass-transistor logic

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353) ◽

10.1109/iscas.2000.856327 ◽

2002 ◽

Author(s):

Shen-Fu Hsiao ◽

Jia-Siang Yeh ◽

Da-Yen Chen

Keyword(s):

High Performance ◽

Logic Synthesis ◽

Pass Transistor ◽

Pass Transistor Logic

High-performance Multiplexer-based Logic Synthesis Using Pass-transistor Logic

VLSI Design ◽

10.1080/1065514021000054736 ◽

2002 ◽

Vol 15 (1) ◽

pp. 417-426 ◽

Cited By ~ 6

Author(s):

Shen-Fu Hsiao ◽

Jia-Siang Yeh ◽

Da-Yen Chen

Keyword(s):

Boolean Functions ◽

High Performance ◽

Voltage Drop ◽

Critical Path ◽

Logic Synthesis ◽

Path Delay ◽

Minimum Width ◽

Pass Transistor ◽

Pass Transistor Logic ◽

Function Sharing

An automatic logic/circuit synthesizer is developed which takes several Boolean functions as input and generates netlist output with basic composing cells from the pass-transistor cell library containing only two types of cells: 2-to-1 multiplexers and inverters. The synthesis procedure first constructs efficient binary decision diagrams (BDDs) for these Boolean functions considering both multi-function sharing and minimum width. Each node in the BDD trees is realized by using a 2-to-1 multiplexer (MUX) of proper driving capability designed pass-transistor logic. The inverters are then inserted all along the MUX paths in order to improve the speed performance and to alleviate the voltage-drop problem. Several methods are proposed to reduce the critical path delay in the multiplexer-chains for generation of faster circuits. Compared to the recently proposed pass-transistor-based top-down design, our synthesizer has better speed and area performance due to the reduced number of cascaded inverters.

Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits

APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems ◽

10.1109/apccas.2006.342077 ◽

2006 ◽

Author(s):

Shen-Fu Hsiao ◽

Ming-Yu Tsai ◽

Chia-Sheng Wen

Keyword(s):

Logic Synthesis ◽

Sequential Circuits ◽

Pass Transistor ◽

Pass Transistor Logic ◽

Efficient Pass

Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction

2008 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2008.4541844 ◽

2008 ◽

Author(s):

Shen-Fu Hsiao ◽

Ming-Yu Tsai ◽

Chia-Sheng Wen

Keyword(s):

Logic Synthesis ◽

Pass Transistor ◽

Pass Transistor Logic

Performance analysis of a two-level carry-skip adder implemented in complementary pass-transistor logic

Microelectronics Journal ◽

10.1016/s0026-2692(98)00043-3 ◽

1998 ◽

Vol 29 (10) ◽

pp. 755-760

Author(s):

Antonio G.M. Strollo ◽

Ettore Napoli

Keyword(s):

Performance Analysis ◽

Pass Transistor ◽

Pass Transistor Logic

An efficient algorithm for low power pass transistor logic synthesis

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design ◽

10.1109/aspdac.2002.994890 ◽

2003 ◽

Cited By ~ 4

Author(s):

R.S. Shelar ◽

S.S. Sapatnekar

Keyword(s):

Low Power ◽

Efficient Algorithm ◽

Logic Synthesis ◽

Pass Transistor ◽

Pass Transistor Logic

Reversed signal propagation BDD based low-power pass-transistor logic synthesis

IEEJ Transactions on Electrical and Electronic Engineering ◽

10.1002/tee.21920 ◽

2013 ◽

Vol 8 (S1) ◽

pp. S66-S71

Author(s):

Thangavel Bhuvaneswari ◽

Vishnuvajjula Charan Prasad ◽

Ajay Kumar Singh

Keyword(s):

Low Power ◽

Logic Synthesis ◽

Signal Propagation ◽

Pass Transistor ◽

Pass Transistor Logic

BDD decomposition for delay oriented pass transistor logic synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2005.853601 ◽

2005 ◽

Vol 13 (8) ◽

pp. 957-970 ◽

Cited By ~ 31

Author(s):

R.S. Shelar ◽

S.S. Sapatnekar

Keyword(s):

Logic Synthesis ◽

Pass Transistor ◽

Pass Transistor Logic

A Binary Decision Diagram Based Cascade Prognostics Scheme For Power Systems

2020 American Control Conference (ACC) ◽

10.23919/acc45564.2020.9147902 ◽

2020 ◽

Author(s):

Ajay Chhokra ◽

Saqib Hasan ◽

Abhishek Dubey ◽

Gabor Karsai

Keyword(s):

Power Systems ◽

Binary Decision Diagram ◽

Binary Decision