An efficient algorithm for low power pass transistor logic synthesis

Reversed signal propagation BDD based low-power pass-transistor logic synthesis

IEEJ Transactions on Electrical and Electronic Engineering ◽

10.1002/tee.21920 ◽

2013 ◽

Vol 8 (S1) ◽

pp. S66-S71

Author(s):

Thangavel Bhuvaneswari ◽

Vishnuvajjula Charan Prasad ◽

Ajay Kumar Singh

Keyword(s):

Low Power ◽

Logic Synthesis ◽

Signal Propagation ◽

Pass Transistor ◽

Pass Transistor Logic

A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL

Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106) ◽

10.1109/aspdac.2000.835065 ◽

2002 ◽

Author(s):

H. Sakamoto ◽

H. Ochi ◽

K. Uda ◽

K. Taki ◽

Bu-Yeol Lee ◽

...

Keyword(s):

Low Power ◽

Pass Transistor ◽

Binary Multiplier ◽

Pass Transistor Logic

A new type of low-power adiabatic circuit with complementary pass-transistor logic

2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03 ◽

10.1109/icasic.2003.1277438 ◽

2003 ◽

Cited By ~ 4

Author(s):

Hu Jianping ◽

Cen Lizhang ◽

Liu Xiao

Keyword(s):

Low Power ◽

Adiabatic Circuit ◽

New Type ◽

Pass Transistor ◽

Pass Transistor Logic

Development and synthesis method for pass-transistor logic family for high-speed and low power CMOS

38th Midwest Symposium on Circuits and Systems. Proceedings ◽

10.1109/mwscas.1995.504436 ◽

2002 ◽

Cited By ~ 7

Author(s):

V.G. Oklobdzija ◽

M. Soderstrand ◽

B. Duchene

Keyword(s):

Low Power ◽

High Speed ◽

Synthesis Method ◽

Low Power Cmos ◽

Pass Transistor ◽

Pass Transistor Logic

Low power 18T pass transistor logic ripple carry adder

IEICE Electronics Express ◽

10.1587/elex.12.20150176 ◽

2015 ◽

Vol 12 (6) ◽

pp. 20150176-20150176 ◽

Cited By ~ 2

Author(s):

Veeraiyah Thangasamy ◽

Noor Ain Kamsani ◽

Mohd Nizar Hamidon ◽

Shaiful Jahari Hashim ◽

Zubaida Yusoff ◽

...

Keyword(s):

Low Power ◽

Ripple Carry Adder ◽

Pass Transistor ◽

Pass Transistor Logic

Low-race Split-level Charge-Recycling Pass-transistor Logic (LSCPL) for low power

Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442) ◽

10.1109/icm.2003.237775 ◽

2003 ◽

Cited By ~ 1

Author(s):

S.H. Rasouli ◽

A. Afzali-Kusha ◽

A. Khademzadeh ◽

M. Nourani

Keyword(s):

Low Power ◽

Charge Recycling ◽

Pass Transistor ◽

Pass Transistor Logic

No-race charge recycling complementary pass transistor logic (NCRCPL) for low power applications

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03. ◽

10.1109/iscas.2003.1206257 ◽

2003 ◽

Cited By ~ 1

Author(s):

A. Abbasian ◽

S. Rasouli ◽

A. Afzali-Kusha ◽

M. Nourani

Keyword(s):

Low Power ◽

Charge Recycling ◽

Pass Transistor ◽

Pass Transistor Logic

High-performance multiplexer-based logic synthesis using pass-transistor logic

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353) ◽

10.1109/iscas.2000.856327 ◽

2002 ◽

Author(s):

Shen-Fu Hsiao ◽

Jia-Siang Yeh ◽

Da-Yen Chen

Keyword(s):

High Performance ◽

Logic Synthesis ◽

Pass Transistor ◽

Pass Transistor Logic

Ultra‐low power pass‐transistor‐logic‐based delay line design for sub‐threshold applications

Electronics Letters ◽

10.1049/el.2016.3240 ◽

2016 ◽

Vol 52 (23) ◽

pp. 1910-1912 ◽

Cited By ~ 2

Author(s):

R.N. Tadros ◽

N. Dasari ◽

P.A. Beerel

Keyword(s):

Low Power ◽

Delay Line ◽

Ultra Low Power ◽

Pass Transistor ◽

Pass Transistor Logic ◽

Line Design

High-performance Multiplexer-based Logic Synthesis Using Pass-transistor Logic

VLSI Design ◽

10.1080/1065514021000054736 ◽

2002 ◽

Vol 15 (1) ◽

pp. 417-426 ◽

Cited By ~ 6

Author(s):

Shen-Fu Hsiao ◽

Jia-Siang Yeh ◽

Da-Yen Chen

Keyword(s):

Boolean Functions ◽

High Performance ◽

Voltage Drop ◽

Critical Path ◽

Logic Synthesis ◽

Path Delay ◽

Minimum Width ◽

Pass Transistor ◽

Pass Transistor Logic ◽

Function Sharing

An automatic logic/circuit synthesizer is developed which takes several Boolean functions as input and generates netlist output with basic composing cells from the pass-transistor cell library containing only two types of cells: 2-to-1 multiplexers and inverters. The synthesis procedure first constructs efficient binary decision diagrams (BDDs) for these Boolean functions considering both multi-function sharing and minimum width. Each node in the BDD trees is realized by using a 2-to-1 multiplexer (MUX) of proper driving capability designed pass-transistor logic. The inverters are then inserted all along the MUX paths in order to improve the speed performance and to alleviate the voltage-drop problem. Several methods are proposed to reduce the critical path delay in the multiplexer-chains for generation of faster circuits. Compared to the recently proposed pass-transistor-based top-down design, our synthesizer has better speed and area performance due to the reduced number of cascaded inverters.