Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage
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2012 ◽
Vol 4
(22)
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pp. 27-36
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2005 ◽
Vol 15
(03)
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pp. 599-614
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1996 ◽
Vol 31
(8)
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pp. 1165-1169
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2011 ◽
Vol 10
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pp. 2470-2475
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2013 ◽
Vol 5
(1)
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pp. 702-710
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