Design and FPGA implementation of a memristor-based multi-scroll hyperchaotic system

In this paper, a novel memristor-based multi-scroll hyperchaotic system is proposed. Based on a voltage-controlled memristor and a modulating sine nonlinear function, a novel method is proposed to generate the multi-scroll hyperchaotic attractors. First, a multi-scroll chaotic system is constructed from a three-dimensional chaotic system by designing a modulating sine nonlinear function. Then, a voltage-controlled memristor is introduced into the above-designed multi-scroll chaotic system. Thus, a memristor-based multi-scroll hyperchaotic system is generated, and this hyperchaotic system can produce various coexisting hyperchaotic attractors with different topological structures. Moreover, different number of scrolls and different topological attractors can be obtained by varying the initial conditions of this system without changing the system parameters. The Lyapunov exponents, bifurcation diagrams and basins of attraction are given to analyze the dynamical characteristics of the multi-scroll hyperchaotic system. Besides, the FPGA-based digital implementation of the memristor-based multi-scroll hyperchaotic system is carried out. The experimental results of the FPGA-based digital circuit are displayed on the oscilloscope.

Neuromorphic Chip Integrated with an LSI and Amorphous-metal-oxide Semiconductor Thin-film Synapse Devices

Artificial intelligences are promising in future societies, and neural networks are typical technologies with the advantages such as self-organization, self-learning, parallel distributed computing, and fault tolerance, but their size and power consumption are large. Neuromorphic systems are biomimetic systems from the hardware level, with the same advantages as living brains, especially compact size, low power, and robust operation, but some well-known ones are non-optimized systems, so the above benefits are only partially gained, for example, machine learning is processed elsewhere to download fixed parameters. To solve these problems, we are researching neuromorphic systems from various viewpoints. In this study, a neuromorphic chip integrated with an LSI and amorphous-metal-oxide semiconductor (AOS) thin-film synapse devices has been developed. The neuron elements are digital circuit, which are made in an LSI, and the synapse devices are analog devices, which are made of the AOS thin film and directly integrated on the LSI. This is the world's first hybrid chip where neuron elements and synapse devices of different functional semiconductors are integrated, and local autonomous learning is utilized, which becomes possible because the AOS thin film can be deposited without heat treatment and there is no damage to the underneath layer, and has all advantages of neuromorphic systems.

Russian healthcare system digitalization: Opportunities and contradictions

The article is devoted to the opportunities and key contradictions of the Russian state healthcare system digitalization project implementation. The authors analyze various aspects of the system digitalization algorithms in light of the federal project “Creation of the Single Digital Circuit in Healthcare based on the Unified State Health Information System”. The aim of the article was to identify problems within goal-setting, documentation development, and practical implementation of the healthcare system digitalization project, as well as to come up with proposals for eliminating these issues. The analysis showed the inefficiency of the expensive healthcare system digitalization project, which has both objective and subjective reasons for its low effectiveness. The authors come to the conclusion that it is necessary to eliminate a number of contradictions and barriers in the framework of the project implementation in order to increase the efficiency of both the healthcare system itself and the high budget federal project of the economy digitalization as a whole. The practical significance of the article consists in the applicability of proposed approach to making the necessary amendments to the current federal project documentation, which will ensure a focus on real needs within the framework of the initiative implementation. The work may be of interest to civil servants, initiators of projects on the healthcare system digital transformation, governmental bodies, healthcare organizations managers, students, and practitioners.

Localization of Hidden Attractors in Chua’s System With Absolute Nonlinearity and Its FPGA Implementation

Investigation of the classical self-excited and hidden attractors in the modified Chua’s circuit is a hot and interesting topic. In this article, a novel Chua’s circuit system with an absolute item is investigated. According to the mathematical model, dynamic characteristics are analyzed, including symmetry, equilibrium stability analysis, Hopf bifurcation analysis, Lyapunov exponents, bifurcation diagram, and the basin of attraction. The hidden attractors are located theoretically. Then, the coexistence of the hidden limit cycle and self-excited chaotic attractors are observed numerically and experimentally. The numerical simulation results are consistent with the FPGA implementation results. It shows that the hidden attractor can be localized in the digital circuit.

Analysis On Power Gating Circuits Based Low Power VLSI Circuits (BCD Adder)

Currently, energy consumption in the digital circuit is a key design parameter for emerging mobile products. The principal cause of the power dissipation during idle mode is leakage currents, which are rising dramatically. Sub-threshold leakage is increased by the scaling of threshold voltage when gate current leakage increases because oxide thickness is scaled. With rising demands for mobile devices, leakage energy consumption has received even greater attention. Since a mobile device spends most of its time in standby mode, leakage power savings need to prolong the battery life. That is why low power has become a significant factor in CMOS circuit design. The required design and simulation of an AND gate with the BSIM4 MOS parameter model at 27 0C, supply voltage of 0,70V with CMOS technology of 65nm are the validation of the suitability of the proposed circuit technology. AND simulation. The performance parameters for the two AND input gate are compared with the current MTCMOS and SCCMOS techniques, such as sub-threshold leakage power dissipations in active and standby modes, the dynamic dissipation, and propagation period. The proposed hybrid super cutoff complete stack technique compared to the current MTCMOS technology shows a reduction in sub-threshold dissipation power dissipation by 3. 50x and 1.15x in standby modes and active modes respectively. The hybrid surface-cutting technique also shows savings of 2,50 and 1,04 in power dissipation at the sub-threshold in standby modes and active modes compared with the existing SCCMOS Technique.

Reversible Gate Logic Adder with Parity Preserving Design

Reversible logic circuits have drawn attention from a variety of fields, including nanotechnology, optical computing, quantum computing, and low-power CMOS design. Low-power and high-speed adder cells (like the BCD adder) are used in binary operation-based electronics. The most fundamental digital circuit activity is binary addition. It serves as a foundation for all subsequent mathematical operations. The main challenge today is to reduce the power consumption of adder circuits while maintaining excellent performance over a wide range of circuit layouts. Error detection in digital systems is aided by parity preservation. This article proposes a concept for a fault-tolerant parity- preserving BCD adder. To reduce power consumption and circuit quantum cost, the proposed method makes use of reversible logic gates like IG, FRG, and F2G. Comparing the proposed circuit to the current counterpart, it has fewer constant inputs and garbage outputting devices and is faster.