scholarly journals Parameter variation analysis for voltage controlled oscillators in phase-locked loops

2008 ◽  
Author(s):  
Igor Vytyaz ◽  
David C. Lee ◽  
Un-Ku Moon ◽  
Kartikeya Mayaram
Keyword(s):  
Parameter Variation ◽  
Phase Locked Loops ◽  
Variation Analysis ◽  
Voltage Controlled Oscillators

NUMERICAL AND EXPERIMENTAL STUDIES OF SELF-SYNCHRONIZATION AND SYNCHRONIZED CHAOS

1992 ◽  
Vol 02 (03) ◽  
pp. 645-657 ◽  
Author(s):  
M. DE SOUSA VIEIRA ◽  
P. KHOURY ◽  
A. J. LICHTENBERG ◽  
M. A. LIEBERMAN ◽  
W. WONCHOBA ◽  
...  
Keyword(s):  
Chaotic Behavior ◽  
Experimental Studies ◽  
Chaotic Signal ◽  
Chaotic Synchronization ◽  
Parameter Variation ◽  
Phase Locked Loops ◽  
Bifurcation Diagrams ◽  
Digital Phase Locked Loops ◽  
Chaotic Carrier ◽  
Good Agreement

We study self-synchronization of digital phase-locked loops (DPLL's) and the chaotic synchronization of DPLL's in a communication system which consists of three or more coupled DPLL's. Triangular wave signals, convenient for experiments, are employed. Numerical and experimental studies of two loops are in good agreement, giving bifurcation diagrams that show quasiperiodic, locked, and chaotic behavior. The approach to chaos does not show the full bifurcation sequence of sinusoidal signals. For studying synchronization to a chaotic signal, the chaotic carrier is generated in a subsystem of two or more self-synchronized DPLL's where one of the loops is stable and the other is unstable. The receiver consists of a stable loop. We verified numerically and experimentally that the receiver may synchronize with the transmitter if the stable loop in the transmitter and receiver are nearly identical and the synchronization degrades with noise and parameter variation. We studied the phase space where synchronization occurs, and quantify the deviation from synchronization using the concept of mutual information.

scholarly journals Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration

2013 ◽  
Vol 2013 ◽  
pp. 1-8 ◽  
Author(s):  
Reza Molavi ◽  
Hormoz Djahanshahi ◽  
Rod Zavari ◽  
Shahriar Mirabbasi
Keyword(s):  
Electromagnetic Coupling ◽  
Phase Locked Loops ◽  
Cmos Process ◽  
Digital Cmos ◽  
Silicon Area ◽  
Voltage Controlled Oscillators ◽  
Process Measurement ◽  
Measurement Results ◽  
Low Jitter ◽  
On Chip

Phase-locked loops (PLLs) employing LC-based voltage-controlled oscillators (LC VCOs) are attractive in low-jitter multigigahertz applications. However, inductors occupy large silicon area, and moreover dense integration of multiple LC VCOs presents the challenge of electromagnetic coupling amongst them, which can compromise their superior jitter performance. This paper presents an analytical model to study the effect of coupling between adjacent LC VCOs when operating in a plesiochronous manner. Based on this study, a low-jitter highly packable clock synthesizer unit (CSU) supporting a continuous (gapless) frequency range up to 5.8 GHz is designed and implemented in a 65 nm digital CMOS process. Measurement results are presented for densely integrated CSUs within a multirate multiprotocol system-on-chip PHY device.

scholarly journals Designing a Ring-VCO for RFID Transponders in 0.18 μm CMOS Process

2014 ◽  
Vol 2014 ◽  
pp. 1-6 ◽  
Author(s):  
Jubayer Jalil ◽  
Mamun Bin Ibne Reaz ◽  
Mohammad Arif Sobhan Bhuiyan ◽  
Labonnah Farzana Rahman ◽  
Tae Gyu Chang
Keyword(s):  
Phase Noise ◽  
Radio Frequency Identification ◽  
Cmos Technology ◽  
Ring Oscillator ◽  
Phase Locked Loops ◽  
Cmos Process ◽  
Voltage Controlled Oscillators ◽  
Delay Cell ◽  
Frequency Identification ◽  
Low Phase Noise

In radio frequency identification (RFID) systems, performance degradation of phase locked loops (PLLs) mainly occurs due to high phase noise of voltage-controlled oscillators (VCOs). This paper proposes a low power, low phase noise ring-VCO developed for 2.42 GHz operated active RFID transponders compatible with IEEE 802.11 b/g, Bluetooth, and Zigbee protocols. For ease of integration and implementation of the module in tiny die area, a novel pseudodifferential delay cell based 3-stage ring oscillator has been introduced to fabricate the ring-VCO. In CMOS technology, 0.18 μm process is adopted for designing the circuit with 1.5 V power supply. The postlayout simulated results show that the proposed oscillator works in the tuning range of 0.5–2.54 GHz and dissipates 2.47 mW of power. It exhibits a phase noise of −126.62 dBc/Hz at 25 MHz offset from 2.42 GHz carrier frequency.

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