Capacitive Boosted Ring Oscillators for All-Digital Phase-Locked Loops (ADPLLs)

Ring oscillator (RO)-based digital phase-locked loops (DPLLs) are very attractive for system-on-chip applications due to their tuning range, good phase noise property but suffer from compactness and power requirements. In this work, the concept of capacitive boosting as one of the key solutions which enhances the amplitude of oscillations of the RO is proposed, making it a suitable solution to the biomedical applications, specifically for medical implant communication system (MICS) band of operation ranging from 400[Formula: see text]MHz to 405[Formula: see text]MHz. With coarse and fine-tuning blocks, this digitally controlled oscillator (DCO) promises a good resolution. The coarse tuning is achieved using conventional MOS capacitors and the fine-tuning is achieved by controlling the fractional metal oxide semiconductor (MOS) capacitances. To benchmark the performance metrics of the single-stage RO in this work, simulations were performed for 680[Formula: see text]mV supply voltage in 45[Formula: see text]nm complementary metal oxide semiconductor (CMOS) technology. The output varies in the range from [Formula: see text]0.422[Formula: see text]V to [Formula: see text][Formula: see text]V, indicating about 224% amplitude enhancement. Despite process voltage temperature (PVT) variations, we can see little impact on the boosted output levels. The designed DCO operates up to a maximum frequency of 495[Formula: see text]MHz at 0.68[Formula: see text]V. The proposed RO has lesser power consumption than any conventional RO, operating at a center frequency of 402[Formula: see text]MHz, thus making it better suitable for the MICS band of applications. Phase noise of [Formula: see text][Formula: see text]dBc/Hz at an offset of 200[Formula: see text]kHz was obtained. The proposed differential DCO consumed power was 95.26[Formula: see text][Formula: see text]W. The figure of merit (FoM) for this DCO is [Formula: see text] (dBc/Hz). The area consumed by the DCO is 0.01872[Formula: see text]mm2.

A Novel Parallel DTC Segmentation Scheme for Fractional-N Digital PLLs

In this paper, we propose a new parallel segmentation scheme for the digital/time converter (DTC) which is employed in fractional-N digital phase-locked loops (PLLs) to cancel out the quantization error induced by the digital DS modulator. The proposed parallel scheme removes one redundant least-mean square (LMS) gain in compared with the conventional parallel one. Therefore, the design of the system becomes less complicated while guaranteeing a fast convergence speed of the LMS gains and a short DTC time range. The effectiveness of the proposed segmentation scheme is demonstrated via simulations of a digital PLL built at behavioral level and compared to the conventional segmentation schemes.

Understanding of the Coherent Demodulation with Phase-Locked Loop

The phase-locked loop (PLL) technology is a very important technology in the communication field. With the development of electronic technology toward digitalization, the phase-locked processing of signal needs to be realized in digital way. Therefore, more and more attentions have been paid to the research and application of all digital phase-locked loops. This paper serves as an introduction about the basic background of PLL, the basic characteristics and structure of PLL, and the basic principles of modulation and demodulation. It provides a concise application about the basic principle and main design process of modulation and demodulation of FSK signal, which are realized by using phase-locked loop chip NE564.