Power Conversion Performance of a Single-Phase PV Inverter with Fuzzy Logic Algorithm

The paper presents a low-power conversion system focusing on implementing new solar inverter control techniques implemented with Fuzzy Logic. The power generated by a solar panel requires robust approaches and efficient methods to be used at its maximum. Therefore, a promising strategy is a Fuzzy Logic based on the Maximum Power Point Tracking (MPPT) algorithm. To gather efficient power conversion, our proposed model uses a control loop composed of Fuzzy Proportional Integrative (PI) regulators, Clarke and Park transform, followed by a synchronization grid mechanism Second-order generalized integrator (SOGI) based phase-locked loops (PLLs). The proposed technique examines photovoltaic system (PV) performance with respect to its non-linearities and eventual shaded conditions that can occur in the PV array. The shading effect is tested by varying the irradiance, which determines the variation of the output current and implicitly of the output power. The simulation results show that the inverter control system is very efficient, generating stable and nearly sinusoidal current and voltage characteristics. Thus, the inverter converts over 99 % of the power generated by PV arrays.

Current mismatch reduction in charge pumps using regulated current stealing-injecting transistors for PLLs

A charge pump for phase locked loops (PLL) with a novel current mismatch compensation technique is proposed. The proposed circuit uses a simple yet effective current stealing-injecting (CSI) technique and feedback to reduce mismatch between the negative-channel-metal-oxide (NMOS) and positive-channel-metal-oxide (PMOS) transistors. The current stealing transistor steals the current from a replica branch and mirrors it to the output where it is added to the output branch by the injecting transistor. A feedback mechanism is used to set the drain voltages of both branches to be equal and mitigate channel length modulation and ensure high accuracy. The proposed circuit was designed on Silterra 130nm technology and simulated using Cadence Spectre. The simulation results show that the proposed circuit yields a maximum of 0.107% and minimum of 0.00465% current mismatch while operating at a low supply voltage of 800mV for a range of 100mV to 700mV. The proposed design uses only one rail-to-rail op amp for compensating the mismatch and an addition of 4 transistors and utilizing 75% of the supply voltage for high voltage controlled oscillator (VCO) tuning range.

On the VCO/Frequency Divider Interface in Cryogenic CMOS PLL for Quantum Computing Applications

The availability of quantum microprocessors is mandatory, to efficiently run those quantum algorithms promising a radical leap forward in computation capability. Silicon-based nanostructured qubits appear today as a very interesting approach, because of their higher information density, longer coherence times, fast operation gates, and compatibility with the actual CMOS technology. In particular, thanks to their phase noise properties, the actual CMOS RFIC Phase-Locked Loops (PLL) and Phase-Locked Oscillators (PLO) are interesting circuits to synthesize control signals for spintronic qubits. In a quantum microprocessor, these circuits should operate close to the qubits, that is, at cryogenic temperatures. The lack of commercial cryogenic Design Kits (DK) may make the interface between the Voltage Controlled Oscillator (VCO) and the Frequency Divider (FD) a serious issue. Nevertheless, currently this issue has not been systematically addressed in the literature. The aim of the present paper is to investigate the VCO/FD interface when the temperature drops from room to cryogenic. To this purpose, physical models of electronics passive/active devices and equivalent circuits of VCO and the FD were developed at room and cryogenic temperatures. The modeling activity has led to design guidelines for the VCO/FD interface, useful in the absence of cryogenic DKs.

A Very Low Reference Spur Phase Offset Technique in Fractional-N Charge pump PLLs

Fractional-N charge pump phase locked loops (PLLs) suffer from the problem of increased in-band phase noise due to charge pump non-linearity caused by UP/DN chargepump current mismatch. Existing techniques that resolve this problem by introducing phase offset between reference and divide signals cause large reference spurs or increase jitter at PLL output. A very low reference spur phase offset technique is proposed in this work. It produces the lowest reference spurs compared to previously published works. A detailed comparison of the reference spurs caused by the different techniques to introduce phase offset is presented. Simulation results show that the reference spur level generated at the PLL output after applying the proposed technique is 26 dB lower than the existing techniques in the presence of 5% chargepump current mismatch.<br>

A Very Low Reference Spur Phase Offset Technique in Fractional-N Charge pump PLLs

Fractional-N charge pump phase locked loops (PLLs) suffer from the problem of increased in-band phase noise due to charge pump non-linearity caused by UP/DN chargepump current mismatch. Existing techniques that resolve this problem by introducing phase offset between reference and divide signals cause large reference spurs or increase jitter at PLL output. A very low reference spur phase offset technique is proposed in this work. It produces the lowest reference spurs compared to previously published works. A detailed comparison of the reference spurs caused by the different techniques to introduce phase offset is presented. Simulation results show that the reference spur level generated at the PLL output after applying the proposed technique is 26 dB lower than the existing techniques in the presence of 5% chargepump current mismatch.<br>

Reference Spur Reduction in Sampled-loop filter PLLs by Oversampling

<div><div><div><p>A technique to completely eliminate reference spurs in both Integer-N and Fractional-N charge pump phase locked loops (PLLs) based on an oversampled loop filter architecture is proposed. A rigorous analysis of the performance of the proposed technique in the presence of implementation non-idealities is also presented. It is shown through analysis and simulations that the proposed technique, in addition to completely eliminating reference spurs, adds an insignificant area and power overhead when applied to Integer-N PLLs and less than 6% increase in area and power in case of Fractional-N PLLs.</p></div></div></div>

Reference Spur Reduction in Sampled-loop filter PLLs by Oversampling

<div><div><div><p>A technique to completely eliminate reference spurs in both Integer-N and Fractional-N charge pump phase locked loops (PLLs) based on an oversampled loop filter architecture is proposed. A rigorous analysis of the performance of the proposed technique in the presence of implementation non-idealities is also presented. It is shown through analysis and simulations that the proposed technique, in addition to completely eliminating reference spurs, adds an insignificant area and power overhead when applied to Integer-N PLLs and less than 6% increase in area and power in case of Fractional-N PLLs.</p></div></div></div>