Differential power analysis (DPA) attack is an important threat that researchers spend great effort to make crypto algorithms resistant against DPA attacks. In order to determine whether the hardware has DPA leakage before manufacturing, an accurate power model in digital simulation has been generated. FPGAs Arrays are attractive options for hardware implementation of encryption algorithms. In this paper, we show generated power model by using integer numbers whole DES’s rounds vs. S-Box alone, and this method gives more realistic results to determine the effectiveness of the improvements protect whole DES rather than in which only informer elements in the DES round. In particular this allows the user to isolate some parts of its implementation in order to analyze information leakages directly linked to them. We review s-box because it’s get 2kbit or 20% CLB slice from FPGA to implement DES or TDES. This paper try to identify role of Sbox in DPA.
Differential Power Analysis resistant hardware implementation of the RSA cryptosystem
