Switching activity reduction in low power Booth multiplier

2008 ◽  
Author(s):  
Rizwan Mudassir ◽  
Mohab Anis ◽  
Javid Jaffari
Keyword(s):  
Low Power ◽  
Switching Activity ◽  
Booth Multiplier ◽  
Switching Activity Reduction

A CLOCK GATED SUCCESSIVE APPROXIMATION REGISTER FOR A/D CONVERSIONS

2014 ◽  
Vol 23 (02) ◽  
pp. 1450023
Author(s):  
MOHAMED O. SHAKER ◽  
MAGDY A. BAYOUMI
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
Power Supply ◽  
Cmos Technology ◽  
Clock Signal ◽  
Switching Activity ◽  
Successive Approximation Register ◽  
Simulation Results ◽  
Data Switching

A novel low power clock gated successive approximation register (SAR) is proposed. The new register is based on gating the clock signal when there is no data switching activity. It operates with fewer transistors and no redundant transitions which makes it suitable for low power applications. The proposed register consisting of 8 bits has been designed up to the layout level with 1 V power supply in 90 nm CMOS technology and has been simulated using SPECTRE. Simulation results have shown that the proposed register saves up to 75% of power consumption.

A Design of Low-Power Bypassing Booth Multiplier

2013 ◽  
Vol 18 (5) ◽  
pp. 67-72
Author(s):  
Jong Hun Ahn ◽  
Seong Rim Choi ◽  
Byeong Gyu Nam
Keyword(s):  
Low Power ◽  
Booth Multiplier
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