Ultra-Low Power and High Sensitivity of Joint Clock Gating Based Dual Feedback Edge Triggered Flip Flop for Biomedical Imaging Applications

To adapt to varied working situations, the latest biomedical imaging applications require low energy consumption, high performance, and extensive energy-performance scalability. State-of-the-art electronics with higher sensitivity, higher counting rate, and finer time resolution are required to create higher precision, higher temporal resolution, and maximum contrast biomedical images. In recent days, the system’s power consumption is important critically in modern VLSI circuits particularly for the low power application. In order to decrease the power, a power optimization technique must be used at various design levels. The low power use of logic cells is a proficient technique for decreasing the circuit level power. Dual Feedback edge triggered Flip Flop (DFETFF) is considered for biomedical imaging applications in the proposed system. Initially, the high dynamic range voltage is given as input signal. The comparator output is then retried at the comparator end. The integration capacitor is employed for storing remaining voltage signal. The comparator voltage is then given to the capacitor reset block. In the proposed work, a capacitor-reset block that employs clock signal takes up a dual-feedbackedge-triggered Flip-flop as an alternative of a conventional type for reducing the final output signals errors. Dual feedback loops assure that feedback loops do not tri-state at the time of SET restoration, a scheme that could lead to SEUs in latches if a single delay component and a single feedback loop are used. In digital system, Clock gating is a competent method of lessening the overall consumption of power along with deactivating the clock signal selectively and is useful for controlling the usage of clock signal asynchronously in reference to input-signal current. The integration-control (Vint) signal is employed in controlling the integration time. On the termination of integration, the signal level phase is kept, also similar one is send to arrangement all through read period. As a result, the simulation was carried out after the design layout and the estimations of performance were made and are compared with traditional approaches to prove the proposed mechanism effectiveness for future biomedical applications.

Experimental FIA Methodology Using Clock and Control Signal Modifications under Power Supply and Temperature Variations

The security of cryptocircuits is determined not only for their mathematical formulation, but for their physical implementation. The so-called fault injection attacks, where an attacker inserts faults during the operation of the cipher to obtain a malfunction to reveal secret information, pose a serious threat for security. These attacks are also used by designers as a vehicle to detect security flaws and then protect the circuits against these kinds of attacks. In this paper, two different attack methodologies are presented based on inserting faults through the clock signal or the control signal. The optimization of the attacks is evaluated under supply voltage and temperature variation, experimentally determining the feasibility through the evaluation of different Trivium versions in 90 nm ASIC technology implementations, also considering different routing alternatives. The results show that it is possible to inject effective faults with both methodologies, improving fault efficiency if the power supply voltage decreases, which requires only half the frequency of the short pulse inserted into the clock signal to obtain a fault. The clock signal modification methodology can be extended to other NLFSR-based cryptocircuits and the control signal-based methodology can be applied to both block and stream ciphers.

Simulation of an Adaptive Method of Improving the Accuracy and Extending the Range of Frequency Signal Processing in a Frequency-to-Code Converter

The article discusses the modification of one of the basic methods of converting successive periods of a variable frequency signal into numerical values representing them. The method performs the adaptive frequency selection of the clock signal in the system processing the consecutive periods of input signal. The signal processing error is analyzed on an ongoing basis, and the frequency change factor is selected. Algorithms describing the operation of the method are included. The program of the simulator of the measurement channel operation with a frequency carrier of information is described, which allows for the verification of the proposed method. Examples of the simulation results are included.

Design of wireless audio transmission system for college English language teaching

In the past, the use of wireless microphone was affected by overload noise, resulting in incomplete transmission of teaching content. In order to solve this problem, a wireless audio transmission system design for College English language teaching is proposed. The overall architecture of SEP6010 wireless voice system is designed, which is output by PWM channel to complete voice playback. UDA1341TS low-power stereo analog-to-digital converter is used to control audio transmission. The voice circuit is designed by adding clock signal or internal programmable clock. The A/D conversion module is used to amplify the collected signal, and the original voice signal is restored through the audio playback module. MATLAB is used to simulate the process of encoding, decoding and filtering. According to CVSD quantization integral coding algorithm, the quantization noise is reduced to a given allowable value. Start Audacity software to complete wireless audio transmission. The experimental results show that the highest transmission teaching content integrity of the system under single frequency input is 98%, and the highest transmission teaching content integrity under mixing input is 93%.

Walking strides direct rapid and flexible recruitment of visual circuits for course control in

Flexible mapping between activity in sensory systems and movement parameters is a hallmark of successful motor control. This flexibility depends on continuous comparison of short-term postural dynamics and the longer-term goals of an animal, thereby necessitating neural mechanisms that can operate across multiple timescales. To understand how such body-brain interactions emerge to control movement across timescales, we performed whole-cell patch recordings from visual neurons involved in course control in Drosophila. We demonstrate that the activity of leg mechanosensory cells, propagating via specific ascending neurons, is critical to provide a clock signal to the visual circuit for stride-by-stride steering adjustments and, at longer timescales, information on speed-associated motor context to flexibly recruit visual circuits for course control. Thus, our data reveal a stride-based mechanism for the control of high-performance walking operating at multiple timescales. We propose that this mechanism functions as a general basis for adaptive control of locomotion.

Two-Stage Clock-Free Time-to-Digital Converter Based on Vernier and Tapped Delay Lines in FPGA Device

This article presents an idea, design and test results of a new time-to-digital converter (TDC) implemented in an FPGA device. The high resolution of 13 ps and measurement range of 3.4 ns are achieved based on a two-stage time interpolation (TI). In the first and second stages of the TI we have used the Vernier delay line and a single tapped delay line, respectively. This solution provides respectable metrological parameters without the need to use a clock signal, and significantly saves the logical resources of an integrated circuit (IC). The proposed method, generally based on two different variants of the discrete delay line, is easy to design and implement in digital ICs. For experimental verification, the TDC was implemented in a single programmable device from family Virtex-7 (Xilinx).

Update on the Phylodynamics of SADS-CoV

Coronaviruses are known to be harmful and heterogeneous viruses, able to infect a large number of hosts. Among them, SADS-CoV (Swine Acute Diarrhea Syndrome Coronavirus), also known as PEAV (Porcine Enteric Alphacoronavirus), or SeA-CoV (Swine Enteric Alphacoronavirus), is the most recent Alphacoronavirus discovered, and caused several outbreaks reported in Chinese swine herds between late 2016 and 2019. We performed an upgraded phylodinamic reconstruction of SADS-CoV based on all whole genomes available on 21 June 2021. Results showed a very close relationship between SADS-CoV and HKU2-like CoV, which may represent the evolutionary intermediate step towards the present SADS-CoV. The direct progenitor of SADS-CoV is so far unknown and, although it is well known that horseshoe bats are reservoirs for Rhinolophus bat coronavirus HKU2-like (HKU2-like CoVs), the transmission path from bats to pigs is still unclear. The discrepancies in the phylogenetic position of rodent CoV, when different molecular markers were considered, corroborate the recombination hypothesis, suggesting that wild rats, which are frequent in farms, may have played a key role. The failure of the attempt at molecular dating, due to the lack of a clock signal, also corroborates the occurrence of a recombination event hypothesis. Zoonotic infections originating in wildlife can easily become a significant threat for human health. In such a context, due to the high recombination and cross-species capabilities of Coronavirus, SADS-CoV represents a possible high-risk pathogen for humans which needs a constant molecular monitoring.

Mitigating Voltage Attacks in Multi-Tenant FPGAs

Recent research has exposed a number of security issues related to the use of FPGAs in embedded system and cloud computing environments. Circuits that deliberately waste power can be carefully crafted by a malicious cloud FPGA user and deployed to cause denial-of-service and fault injection attacks. The main defense strategy used by FPGA cloud services involves checking user-submitted designs for circuit structures that are known to aggressively consume power. Unfortunately, this approach is limited by an attacker’s ability to conceive new designs that defeat existing checkers. In this work, our contributions are twofold. We evaluate a variety of circuit power wasting techniques that typically are not flagged by design rule checks imposed by FPGA cloud computing vendors. The efficiencies of five power wasting circuits, including our new design, are evaluated in terms of power consumed per logic resource. We then show that the source of voltage attacks based on power wasters can be identified. Our monitoring approach localizes the attack and suppresses the clock signal for the target region within 21 μs, which is fast enough to stop an attack before it causes a board reset. All experiments are performed using a state-of-the-art Intel Stratix 10 FPGA.

Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance

The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining its performance. One parameter that causes the degradation effect is the delay occurrence caused by the hot carrier injection and negative bias temperature instability. As such, this research proposed a multipoint detection technique that detects the delay occurrence caused by the hot carrier injection and negative bias temperature instability degradation effects. The multipoint detection technique also assisted in signaling the aging effect on the field-programmable gate array caused by the delay occurrence. The multipoint detection technique was also integrated with a method to optimize the performance of the field-programmable gate array via an automatic clock correction scheme, which could provide the best clock signal for prolonging the field-programmable gate array performance that degraded due to the degradation effect. The delay degradation effect ranged from 0° to 360° phase shifts that happened in the field-programmable gate array as an input feeder into the multipoint detection technique. With the ability to provide closed-loop feedback, the proposed multipoint detection technique offered the best clock signal to prolong the field-programmable gate array performance. The results obtained using the multipoint detection technique could detect the remaining lifetime of the field-programmable gate array and propose the best possible signal to prolong the field-programmable gate array’s performance. The validation showed that the multipoint detection technique could prolong the performance of the degraded field-programmable gate array by 13.89%. With the improvement shown using the multipoint detection technique, it was shown that compensating for the degradation effect of the field-programmable gate array with the best clock signal prolonged the performances.