VLSI Architecture of High Speed SAD for High Efficiency Video Coding (HEVC) Encoder

2018 ◽  
Author(s):  
Amit M. Joshi ◽  
Mohd. Samar Ansari ◽  
Chitrakant Sahu
Keyword(s):  
Video Coding ◽  
High Speed ◽  
High Efficiency ◽  
Vlsi Architecture ◽  
High Efficiency Video Coding

scholarly journals Design of High Speed H.265 Sample Adaptive Offset Estimation for Ultra Hd Tv Encoding using Clock Synchronization Code

2019 ◽  
Vol 8 (2) ◽  
pp. 719-724
Keyword(s):  
Video Coding ◽  
High Speed ◽  
High Efficiency ◽  
Clock Synchronization ◽  
High Efficiency Video Coding ◽  
Heterogeneous Information ◽  
And Control ◽  
Information Streams ◽  
Width Reduction ◽  
Range Selection

Sample adaptive offset (SAO) is a recently presented in-circle separating segment in H.265/High Efficiency Video Coding (HEVC). SAO adds to a striking coding effectiveness enhancement; the estimation of SAO parameters commands the multifaceted nature of in-circle sifting in HEVC encoding. Double clock engineering that procedures statistics collection (SC) and parameter decision (PD), the two principle useful squares of SAO estimation, at high-and low-speed timekeepers, separately. Such a technique decreases the general zone by 56% by tending to the heterogeneous information streams of SC and PD. This exploration work endeavors to ad lib the working clock speed by adjusting a double clock synchronizer VLSI structure of H.265 ultra HD encoder and control minimization. To additionally enhance the territory and power productivity, calculation engineering co-improvements are connected, including a coarse range selection (CRS) and an accumulator bit width reduction (ABR). They together may accomplish another 25% territory decrease. The proposed VLSI configuration is fit for handling 8k at 120-outlines/s encoding

High-Performance Hardware Interpolation Architecture for High Efficiency Video Coding Decoder

2016 ◽  
Vol 11 (9) ◽  
pp. 764
Author(s):  
Lella Aicha Ayadi ◽  
Nihel Neji ◽  
Hassen Loukil ◽  
Mouhamed Ali Ben Ayed ◽  
Nouri Masmoudi
Keyword(s):  
Video Coding ◽  
High Performance ◽  
High Efficiency ◽  
High Efficiency Video Coding

scholarly journals A low-area high-efficiency video coding inverse transform core using resource and time sharing architecture

2020 ◽  
Vol 2020 (1) ◽  
Author(s):  
Yuan-Ho Chen ◽  
Chieh-Yang Liu
Keyword(s):  
Video Coding ◽  
Large Scale ◽  
High Efficiency ◽  
Vlsi Design ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Time Sharing ◽  
High Efficiency Video Coding ◽  
Low Area ◽  
Matrix Products

AbstractIn this paper, a very-large-scale integration (VLSI) design that can support high-efficiency video coding inverse discrete cosine transform (IDCT) for multiple transform sizes is proposed. The proposed two-dimensional (2-D) IDCT is implemented at a low area by using a single one-dimensional (1-D) IDCT core with a transpose memory. The proposed 1-D IDCT core decomposes a 32-point transform into 16-, 8-, and 4-point matrix products according to the symmetric property of the transform coefficient. Moreover, we use the shift-and-add unit to share hardware resources between multiple transform dimension matrix products. The 1-D IDCT core can simultaneously calculate the first- and second-dimensional data. The results indicate that the proposed 2-D IDCT core has a throughput rate of 250 MP/s, with only 110 K gate counts when implemented into the Taiwan semiconductor manufacturing (TSMC) 90-nm complementary metal-oxide-semiconductor (CMOS) technology. The results show the proposed circuit has the smallest area supporting the multiple transform sizes.

Co‐design implementation of High Efficiency Video Coding standard encoder on Zynq MPSoC

2021 ◽  
Vol 49 (4) ◽  
pp. 1013-1027
Author(s):  
Hajar Touzani ◽  
Anass Mansouri ◽  
Fatima Errahimi ◽  
Ali Ahaitouf
Keyword(s):  
Video Coding ◽  
High Efficiency ◽  
High Efficiency Video Coding
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