Low-Power and Area-Efficient Finite Field Multiplier Architecture Based on Irreducible All-One Polynomials

2020 ◽  
Author(s):  
Shima Mohaghegh ◽  
Gurtac Yemiscioglu ◽  
Ali Muhtaroglu
Keyword(s):  
Finite Field ◽  
Low Power ◽  
Finite Field Multiplier ◽  
Area Efficient

scholarly journals Design of High Speed and Area Efficient Finite Field Multiplier Using Factoring Technique for Communication

2021 ◽  
Vol 2089 (1) ◽  
pp. 012071
Author(s):  
S Baba Fariddin ◽  
Rahul Mishra
Keyword(s):  
Finite Field ◽  
Data Security ◽  
High Speed ◽  
Input Data ◽  
Present Generation ◽  
Finite Field Multiplier ◽  
Simulation Results ◽  
Area Efficient

Abstract In this paper, design of high speed and area efficient finite field multiplier using factoring technique for communication is implemented. Data security plays very important role in present generation. Therefore, initially inputs and key are given to S-Box. The main intent of S-Box is to substitute the input data and key. After that input data and key are merged using S-Box merge. This data will be multiplied using finite field multiplier and to improve the performance along with that mix column technique is applied. Factoring technique will increase the speed of operation. After the data performs shift row operation. At last rounding is performed to the obtained data. At last simulation results shows that effective outcome in terms of delay, memory and security.

Low-Power and Area-Efficient Approximate Parallel Design Using Bypassing

2019 ◽  
Author(s):  
Anushka Prakash B ◽  
Noah Kiran Nandi ◽  
Marimuthu R ◽  
Balamurugan S ◽  
Duraivel A.N.
Keyword(s):  
Low Power ◽  
Parallel Design ◽  
Area Efficient

Performance Analysis of an Area Efficient and Low Power MOD-R2MDC FFT for MIMO OFDM

2014 ◽  
Vol 573 ◽  
pp. 176-180
Author(s):  
G. Kavitha ◽  
B. Kirthiga ◽  
N. Kirubanandasarathy
Keyword(s):  
Low Power ◽  
Orthogonal Frequency Division Multiplexing ◽  
Ofdm System ◽  
Description Language ◽  
Fft Processor ◽  
Synthesis Tool ◽  
Mimo Ofdm ◽  
Hardware Description ◽  
Fft Algorithms ◽  
Area Efficient

In this paper, an area-efficient low power fast fourier transform (FFT) processor is proposed for multi input multi output-orthogonal frequency division multiplexing (MIMO-OFDM) in wireless communication system. It consists of a modified architecture of radix-2 algorithm which is described as modified radix-2 multipath delay commutation (MOD-R2MDC). The OFDM receiver with modified R2MDC (MOD-R2MDC) FFT was designed by Hardware Description Language (HDL) coding The Xilinx ISE Design Suite 10.1 is used as a synthesis tool for getting the power and area. The Model-Sim 6.3c is used for simulation. Also the existing OFDM system has been tested with these FFT algorithms and their performances were analyzed with respect to occupancy area in FPGA and power consumption. A low-power and area efficient architecture enables the real-time operations of MIMO OFDM system.

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