scholarly journals Design of High Speed and Area Efficient Finite Field Multiplier Using Factoring Technique for Communication

2021 ◽  
Vol 2089 (1) ◽  
pp. 012071
Author(s):  
S Baba Fariddin ◽  
Rahul Mishra
Keyword(s):  
Finite Field ◽  
Data Security ◽  
High Speed ◽  
Input Data ◽  
Present Generation ◽  
Finite Field Multiplier ◽  
Simulation Results ◽  
Area Efficient

Abstract In this paper, design of high speed and area efficient finite field multiplier using factoring technique for communication is implemented. Data security plays very important role in present generation. Therefore, initially inputs and key are given to S-Box. The main intent of S-Box is to substitute the input data and key. After that input data and key are merged using S-Box merge. This data will be multiplied using finite field multiplier and to improve the performance along with that mix column technique is applied. Factoring technique will increase the speed of operation. After the data performs shift row operation. At last rounding is performed to the obtained data. At last simulation results shows that effective outcome in terms of delay, memory and security.

High speed VLSI implementation of a finite field multiplier using redundant representation

2009 ◽  
Author(s):  
Ashkan Hosseinzadeh Namin ◽  
Karl Leboeuf ◽  
Roberto Muscedere ◽  
Huapeng Wu ◽  
Majid Ahmadi
Keyword(s):  
Finite Field ◽  
High Speed ◽  
Vlsi Implementation ◽  
Finite Field Multiplier ◽  
Redundant Representation

scholarly journals A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop in 55 nm MTCMOS

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 802
Author(s):  
Heng You ◽  
Jia Yuan ◽  
Weidi Tang ◽  
Zenghui Yu ◽  
Shushan Qiao
Keyword(s):  
Low Power ◽  
High Speed ◽  
Input Data ◽  
Low Voltage ◽  
Flip Flop ◽  
Sense Amplifier ◽  
Low Voltage Operation ◽  
Amplifier Stage ◽  
Simulation Results ◽  
Power Delay Product

In this paper, a sense-amplifier-based flip-flop (SAFF) suitable for low-power high-speed operation is proposed. With the employment of a new sense-amplifier stage as well as a new single-ended latch stage, the power and delay of the flip-flop is greatly reduced. A conditional cut-off strategy is applied to the latch to achieve glitch-free and contention-free operation. Furthermore, the proposed SAFF can provide low voltage operation by adopting MTCMOS optimization. Post-layout simulation results based on a SMIC 55 nm MTCMOS show that the proposed SAFF achieves a 41.3% reduction in the CK-to-Q delay and a 36.99% reduction in power (25% input data toggle rate) compared with the conventional SAFF. Additionally, the delay and the power are smaller than those of the master-slave flip-flop (MSFF). The power-delay-product of the proposed SAFF shows 2.7× and 3.55× improvements compared with the conventional SAFF and MSFF, respectively. The area of the proposed flip-flop is 8.12 μm2 (5.8 μm × 1.4 μm), similar to that of the conventional SAFF. With the employment of MTCMOS optimization, the proposed SAFF could provide robust operation even at supply voltages as low as 0.4 V.

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