High speed FPGA implementation of RSA encryption algorithm

2004 ◽  
Author(s):  
O. Nibouche ◽  
M. Nibouche ◽  
A. Bouridane
Keyword(s):  
High Speed ◽  
Fpga Implementation ◽  
Encryption Algorithm

A Novel Image Encryption Algorithm Using Multiple Encryption Techniques for Mobile Devices

2020 ◽  
Vol 10 (2) ◽  
pp. 123-142
Author(s):  
Showkat Ahmad Bhat ◽  
Amandeep Singh
Keyword(s):  
Wireless Communication ◽  
Communication Networks ◽  
Image Encryption ◽  
High Speed ◽  
Security Analysis ◽  
Encryption Algorithm ◽  
Multiple Encryption ◽  
Communication Devices ◽  
Cryptographic Attacks ◽  
Image Encryption Algorithm

Background & Objective: Digital multimedia exchange between different mobile communication devices has increased rapidly with the invention of the high-speed data services like LTE-A, LTE, and WiMAX. However, there are always certain security risks associated with the use of wireless communication technologies. Methods: To protect the digital images against cryptographic attacks different image encryption algorithms are being employed in the wireless communication networks. These algorithms use comparatively less key spaces and accordingly offer inadequate security. The proposed algorithm described in this paper based on Rubik’s cube principle because of its high confusion and diffusion properties, Arnold function having effective scrambling power, blocking cipher with block encryption and permutation powers. The main strength of the proposed algorithm lies in the large key spaces and the combination of different high power encryption techniques at each stage of algorithm. The different operations employed on the image are with four security keys of different key spaces at multiple stages of the algorithm. Results & Conclusion: Finally, the effectiveness and the security analysis results shows that the proposed image encryption algorithm attains high encryption and security capabilities along with high resistance against cryptanalytic attacks, differential attacks and statistical attacks.

AES-128 Cipher. High Speed, Low Cost FPGA Implementation

2007 ◽  
Author(s):  
Monica Liberatori ◽  
Fernando Otero ◽  
J. C. Bonadero ◽  
Jorge Castineira
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Fpga Implementation

High-speed parallel matched filter designing and FPGA implementation

2010 ◽  
Vol 15 (4) ◽  
pp. 335-339
Author(s):  
Qinglin Zhang ◽  
Shuzhen Chen ◽  
Yijun Luo ◽  
Shan Wang
Keyword(s):  
High Speed ◽  
Matched Filter ◽  
Fpga Implementation
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