Adaptive HTTP Streaming Utilizing Temporal Sub-layers of High Efficiency Video Coding (HEVC)

2013 ◽  
Author(s):  
Sachin Deshpande
Keyword(s):  
Video Coding ◽  
High Efficiency ◽  
High Efficiency Video Coding ◽  
Adaptive Http Streaming ◽  
Http Streaming

Adaptive HTTP Streaming with Temporal Scalability in High Efficiency Video Coding (HEVC)

2014 ◽  
Vol 08 (02) ◽  
pp. 229-243
Author(s):  
Sachin Deshpande
Keyword(s):  
Video Coding ◽  
High Efficiency ◽  
Switching Behavior ◽  
High Efficiency Video Coding ◽  
Temporal Scalability ◽  
Server Side ◽  
Adaptive Http Streaming ◽  
Streaming Algorithm ◽  
Http Streaming

The newly approved High Efficiency Video Coding Standard (HEVC) includes temporal sub-layering feature, which provides temporal scalability. Two types of pictures — Temporal Sub-layer Access Pictures and Step-wise Temporal Sub-layer Access Pictures are provided for this purpose. This paper utilizes the temporal scalability in HEVC to provide bandwidth adaptive HTTP streaming. We describe our HTTP streaming algorithm, which is media timeline aware and which dynamically switches temporal sub-layers on the server side. We performed subjective tests to determine user perception regarding acceptable frame rates when using temporal scalability of HEVC. These results are used to control the algorithm's temporal switching behavior to provide a good quality of experience to the user. We applied Internet and 3GPP error-delay patterns to validate the performance of our algorithm.

scholarly journals Evaluation of H.265 Video Delivery Based on Dynamic Adaptive Streaming over HTTP (DASH) Using Mobile Devices

2017 ◽  
Vol 1 (2) ◽  
Author(s):  
Hamid Azwar
Keyword(s):  
Video Coding ◽  
Mobile Devices ◽  
High Efficiency ◽  
Video Quality ◽  
Video Segment ◽  
Adaptive Streaming ◽  
Video Delivery ◽  
High Efficiency Video Coding ◽  
3G Networks ◽  
Http Streaming

MPEG Dynamic Adaptive Streaming over HTTP (MPEG-DASH) is a standard for HTTP streaming that allows interoperability between servers and clients from different vendors which is able to adjust the speed of video delivery to changing bandwidth. Today there is the latest H.265 video coding known as the High Efficiency Video Coding (HEVC). This research implemented the delivery of the H.265 video through the method of Dynamic Adaptive Streaming over HTTP (DASH) using mobile devices. The test was conducted by sending videos over 3G networks with GSM length video segment consists of 2 seconds, 5 seconds, 10 seconds and 20 seconds. The video quality provided in this study consisted of 5 video levels with different bit rates. From the test results, the submitted videos using a smaller video segment generated greater throughput and acquired more video quality with a higher bit rate than the video to a larger segment. Video delivery with segment of 2 seconds acquired video quality with the highest level of 83%, meanwhile the video delivery segment of 20 seconds obtained video quality with the highest level of 33%.

High-Performance Hardware Interpolation Architecture for High Efficiency Video Coding Decoder

2016 ◽  
Vol 11 (9) ◽  
pp. 764
Author(s):  
Lella Aicha Ayadi ◽  
Nihel Neji ◽  
Hassen Loukil ◽  
Mouhamed Ali Ben Ayed ◽  
Nouri Masmoudi
Keyword(s):  
Video Coding ◽  
High Performance ◽  
High Efficiency ◽  
High Efficiency Video Coding

scholarly journals A low-area high-efficiency video coding inverse transform core using resource and time sharing architecture

2020 ◽  
Vol 2020 (1) ◽  
Author(s):  
Yuan-Ho Chen ◽  
Chieh-Yang Liu
Keyword(s):  
Video Coding ◽  
Large Scale ◽  
High Efficiency ◽  
Vlsi Design ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Time Sharing ◽  
High Efficiency Video Coding ◽  
Low Area ◽  
Matrix Products

AbstractIn this paper, a very-large-scale integration (VLSI) design that can support high-efficiency video coding inverse discrete cosine transform (IDCT) for multiple transform sizes is proposed. The proposed two-dimensional (2-D) IDCT is implemented at a low area by using a single one-dimensional (1-D) IDCT core with a transpose memory. The proposed 1-D IDCT core decomposes a 32-point transform into 16-, 8-, and 4-point matrix products according to the symmetric property of the transform coefficient. Moreover, we use the shift-and-add unit to share hardware resources between multiple transform dimension matrix products. The 1-D IDCT core can simultaneously calculate the first- and second-dimensional data. The results indicate that the proposed 2-D IDCT core has a throughput rate of 250 MP/s, with only 110 K gate counts when implemented into the Taiwan semiconductor manufacturing (TSMC) 90-nm complementary metal-oxide-semiconductor (CMOS) technology. The results show the proposed circuit has the smallest area supporting the multiple transform sizes.

Co‐design implementation of High Efficiency Video Coding standard encoder on Zynq MPSoC

2021 ◽  
Vol 49 (4) ◽  
pp. 1013-1027
Author(s):  
Hajar Touzani ◽  
Anass Mansouri ◽  
Fatima Errahimi ◽  
Ali Ahaitouf
Keyword(s):  
Video Coding ◽  
High Efficiency ◽  
High Efficiency Video Coding
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