Abstract
Rapidly changing technology highlights the necessity of developing new failure analysis methodologies. This paper will discuss the combination of two techniques, Design for Test (DFT) and Focused Ion Beam (FIB) analysis, as a means for successfully isolating and identifying a series of high impedance failure sites in a 0.35 μm CMOS design. Although DFT was designed for production testing, the failure mechanism discussed in this paper may not have been isolated without this technique. The device of interest is a mixed signal integrated circuit that provides a digital up-convert function and quadrature modulation. The majority of the circuit functions are digital and as such the majority of the die area is digital. For this analysis, Built In Self Test (BIST) circuitry, an evaluation board for bench testing and FIB techniques were used to successfully identify an unusual failure mechanism. Samples were subjected to Highly Accelerated Stress Test (HAST) as part of the device qualification effort. Post-HAST electrical testing at 200MHz indicated that two units were non-functional. Several different functional blocks on the chip failed electrical testing. One part of the circuitry that failed was the serial interface. The failure analysis team decided to look at the serial interface failure mode first because of the simplicity of the test. After thorough analysis the FA team discovered increasing the data setup time at the serial port input allowed the device to work properly. SEM and FIB techniques were performed which identified a high impedance connection between a metal layer and the underlying via layer. The circuit was modified using a FIB edit, after which all vectors were read back correctly, without the additional set-up time.
Verification Platform of 40Gbps High-speed Serial Interface Chip Based on UVM