A CMOS ethernet serial interface chip

Author(s):  
Haw-Ming Haung ◽  
D. Banatao ◽  
G. Perlegos ◽  
Tsing-Ching Wu ◽  
Te-Long Chiu
Author(s):  
Alan Kennen ◽  
John F. Guravage ◽  
Lauren Foster ◽  
John Kornblum

Abstract Rapidly changing technology highlights the necessity of developing new failure analysis methodologies. This paper will discuss the combination of two techniques, Design for Test (DFT) and Focused Ion Beam (FIB) analysis, as a means for successfully isolating and identifying a series of high impedance failure sites in a 0.35 μm CMOS design. Although DFT was designed for production testing, the failure mechanism discussed in this paper may not have been isolated without this technique. The device of interest is a mixed signal integrated circuit that provides a digital up-convert function and quadrature modulation. The majority of the circuit functions are digital and as such the majority of the die area is digital. For this analysis, Built In Self Test (BIST) circuitry, an evaluation board for bench testing and FIB techniques were used to successfully identify an unusual failure mechanism. Samples were subjected to Highly Accelerated Stress Test (HAST) as part of the device qualification effort. Post-HAST electrical testing at 200MHz indicated that two units were non-functional. Several different functional blocks on the chip failed electrical testing. One part of the circuitry that failed was the serial interface. The failure analysis team decided to look at the serial interface failure mode first because of the simplicity of the test. After thorough analysis the FA team discovered increasing the data setup time at the serial port input allowed the device to work properly. SEM and FIB techniques were performed which identified a high impedance connection between a metal layer and the underlying via layer. The circuit was modified using a FIB edit, after which all vectors were read back correctly, without the additional set-up time.


Author(s):  
D. Walters ◽  
P. Lou ◽  
O. Fanini ◽  
P. Koeppen
Keyword(s):  

2012 ◽  
Vol 220-223 ◽  
pp. 2903-2907
Author(s):  
Xiu Juan Zhang ◽  
Jia Ming Luan ◽  
Li Na Ni

This paper introduces the design of PDF417 two-dimensional barcode digital watermarking system with SOPC chip EP2C70F896C6 made by Alters fully. Analyzed structure and working principle of the hardware and software. System used video conversion chip VGA of DE2-70 development board made by Terasic Technologies and PCI bus interface chip SD card, realized the barcode watermark control with Verilog HDL and C language common programming. The system has many merits such as high velocity, good commonality and low costs etc.


2014 ◽  
Vol 986-987 ◽  
pp. 2078-2081
Author(s):  
Wei Wei ◽  
Fei Teng Zhang

Analysis the characteristics of the measured transmission signal of Mobile Industry Processor Interface (MIPI) Display Serial Interface Physical Layer (D-PHY) interface based on a project platform. Firstly, introduces the transmission characteristics and mutual conversion process of physical layer about high-speed and low power mode, and by the transmission signal measured a platform of high-speed mode, present the D-PHY transmission signal each test items and test point selection, make the phone run smoothly and screen display normally, this test analysis certain practicability and expansibility.


Author(s):  
Hyun-Kyu Jeon ◽  
Hye-Ran Kim ◽  
Jung-Min Choi ◽  
Ju-Pyo Hong ◽  
Yong-Suk Kim ◽  
...  

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