Droplet Transportation through an Orifice on Electrode for Digital Microfluidics Modulations

A digital microfluidic modular interface (chip-to-chip interface) which possesses an electrode with an orifice to vertically transport core–shell droplets is presented. The electrodes were geometrically designed to promote droplet deformation and suspension. The droplets were then applied with an electrical potential for insertion into and passage through the orifice. The concepts were tested with three types of droplets at the volume of 0.75~1.5 μL, which is usually difficult to transfer through an orifice. The integration of electrowetting on dielectric (EWOD) with paper-based microfluidics was demonstrated: the droplet could be transported within 10 s. More importantly, most of the core droplet (~97%) was extracted and passed through with only minimal shell droplets accompanying it.

Embedded Hardware Circuit and Software Development of USB based Hardware Accelerator

<p>This paper focus on design and develop a Hardware Accelerator which can plug in to Universal Serial Bus of any modern low power low cost embedded development system to do complex processing in a plug and play development environment. Cryptographic algorithms, steganography and encoding decoding applications can use co-devices to accelerate performance. In this paper an implementation of a hardware infrastructure for computing though USB bus of any small scale embedded controller board. Execution engine of the accelerator will be an FPGA which is connected to a USB controller with DDR memory to store user data. FPGAs can perform the process faster than low power microcontrollers to solve such algorithms. For the implementation XILINX ARTIX 7 FPGA is used to off load the algorithm for faster processing. System also has a Cypress USB interface chip for offloading data path. Hardware also has a DRAM memory for dumping the data to be stored. Design also explores different futuristic features like interrupt connection for faster response path, shared memory architecture for hand shake mechanism and GPIO connection for implementation of faster interfaces for IO expansion.</p>

A New Package for High Speed and High Density eStorage Using the Frequency Boosting Chip

A die-stacking technology in a multi-chip package can effectively increase the capacity. However, long wire bonding for multi-chip stack, inter-symbol interference caused by large capacitive loading and I/O speed degradations due to simultaneous switching noise (SSN) and power consumption have become obstacles to optimize the internal NAND flash interface. In this paper, to overcome the inevitable challenge between larger storage capacity and higher I/O speed, we propose a new package structure with a frequency boosting interface chip (FBI-chip) for high speed and high density eStorage.