Identification of Yield Limiting Defects in a 0.5 Micron, Shallow Trench Isolation Technology

During the development and qualification of a radiation-hardened, 0.5 μm shallow trench isolation technology, several yield-limiting defects were observed. The 256K (32K x 8) static-random access memories (SRAMs) used as a technology characterization vehicle had elevated power supply current during wafer probe testing. Many of the die sites were functional, but exhibited quiescent power supply current (IDDQ) in excess of 100 μA, the present limit for this particular SRAM. Initial electrical analysis indicated that many of the die sites exhibited unstable IDDQ that fluctuated rapidly. We refer to this condition as “jitter.” The IDDQ jitter appeared to be independent of temperature and predominately associated with the larger 256K SRAMs and not as prevalent in the 16K SRAMs (on the same reticle set). The root cause of failure was found to be two major processing problems: salicide bridging and stress-induced dislocations in the silicon island

Latch-Up Induced Slit Voiding in Aluminum Metal Lines

Latch-up induced during High Temperature Operating Life (HTOL) test of a mixed signal device fabricated with 1.0 μm CMOS, double poly, double metal process caused failures due to an open in aluminum metal line. Metal lines revealed wedge voids of about 50% of the line width. Triggering of latch up mechanism during the HTOL test resulted in a several fold increase of current flowing through the ground metal line. This increase in current resulted in the growth of the wedge voids leading to failures due to open metal lines.

Infrared Emission Spectroscopy as a Reliability Tool

In this paper, we report on a non-destructive technique, based on IR emission spectroscopy, for measuring the temperature of a hot spot in the gate channel of a GaAs metal/semiconductor field effect transistor (MESFET). A submicron-size He-Ne laser provides the local excitation of the gate channel and the emitted photons are collected by a spectrophotometer. Given the state of our experimental test system, we estimate a spectral resolution of approximately 0.1 Angstroms and a spatial resolution of approximately 0.9 μm, which is up to 100 times finer spatial resolution than can be obtained using the best available passive IR systems. The temperature resolution (<0.02 K/μm in our case) is dependent upon the spectrometer used and can be further improved. This novel technique can be used to estimate device lifetimes for critical applications and measure the channel temperature of devices under actual operating conditions. Another potential use is cost-effective prescreening for determining the 'hot spot' channel temperature of devices under normal operating conditions, which can further improve device design, yield enhancement, and reliable operation. Results are shown for both a powered and unpowered MESFET, demonstrating the strength of our infrared emission spectroscopy technique as a reliability tool.

Electrical Probing and Surface Imaging of Deep Sub-Micron Integrated Circuits

A contact probing system for surface imaging and real-time signal measurement of deep sub-micron integrated circuits is discussed. The probe fits on a standard probe-station and utilizes a conductive atomic force microscope tip to rapidly measure the surface topography and acquire real-time highfrequency signals from features as small as 0.18 micron. The micromachined probe structure minimizes parasitic coupling and the probe achieves a bandwidth greater than 3 GHz, with a capacitive loading of less than 120 fF. High-resolution images of submicron structures and waveforms acquired from high-speed devices are presented.

Correlation of Electronic and Thermal Properties of Short Channel nMOSFETS

Light emission and heat generation of Si devices have become important in understanding physical phenomena in device degradation and breakdown mechanisms. This paper correlates the photon emission with the temperature distribution of a short channel nMOSFET. Investigations have been carried out to localize and characterize the hot spots using a spectroscopic photon emission microscope and a scanning thermal microscope. Frontside investigations have been carried out and are compared and discussed with backside investigations. A method has been developed to register the backside thermal image with the backside illuminated image.

Electromigration and Electrochemical Reaction Mixed Failure Mechanism in Gold Interconnection System

Power bipolar devices with gold metallization experience high failure rates. The failures are characterized as shorts, detected during LSI testing at burn-in. Many of these shorted locations are the same for the failed devices. From a statistical lot analysis, it is found that the short failure rate is higher for devices with thinner interlayer dielectric films. Based upon these results, a new electromigration and electrochemical reaction mixed failure mechanism is proposed for the failure.

Current-Signature-Based Analysis of Complex Test Fails

This article provides an analysis of a class of failures observed during the SEMATECH-sponsored Test Methods Experiment. The analysis focuses on use of test-based failure analysis and IDDQ signature analysis to gain insight into the physical mechanisms underlying such subtle failures. In doing so, the analysis highlights techniques for understanding failure mechanisms using only tester data. In the experiment, multiple test methods were applied to a 0.45 micrometer effective channel length ASIC. Specifically, ICs that change test behavior from before to after burn-in are studied to understand the physical nature of the mechanism underlying their failure. Examples of the insights provided by the test-based analysis include identifying cases where there are multiple or complex defects and distinguishing cases where the defect type is likely to be a short versus an open and determining if the defect is marginal. These insights can be helpful for successful failure analysis.

BGA and Advanced Package Wire to Wire Bonding for Backside Emission Microscopy

A new method of preparation will be shown which allows traditional fixturing such as test heads and probe stations to be utilized in a normal test mode. No inverted boards cabled to a tester are needed since the die remains in its original package and is polished and rebonded to a new package carrier with the polished side facing upward. A simple pin reassignment is all that is needed to correct the reverse wire sequence after wire to wire bonding or wire to frame bonding in the new package frame. The resulting orientation eliminates many of the problems of backside microscopy since the resulting package orientation is now frontside. The low profile as a result of this technique allows short working distance objectives such as immersion lenses to be used across the die surface. Test equipment can be used in conjunction with analytical tools such as the emission microscope or focused ion beam due to the upright orientation of the polished backside silicon. The relationship between silicon thickness and transmission for various wavelengths of light will be shown. This preparation technique is applicable to advanced packaging methods and has the potential to become part of future assembly processes.

Investigation of High Frequency Failures on a 0.35μm CMOS IC

Rapidly changing technology highlights the necessity of developing new failure analysis methodologies. This paper will discuss the combination of two techniques, Design for Test (DFT) and Focused Ion Beam (FIB) analysis, as a means for successfully isolating and identifying a series of high impedance failure sites in a 0.35 μm CMOS design. Although DFT was designed for production testing, the failure mechanism discussed in this paper may not have been isolated without this technique. The device of interest is a mixed signal integrated circuit that provides a digital up-convert function and quadrature modulation. The majority of the circuit functions are digital and as such the majority of the die area is digital. For this analysis, Built In Self Test (BIST) circuitry, an evaluation board for bench testing and FIB techniques were used to successfully identify an unusual failure mechanism. Samples were subjected to Highly Accelerated Stress Test (HAST) as part of the device qualification effort. Post-HAST electrical testing at 200MHz indicated that two units were non-functional. Several different functional blocks on the chip failed electrical testing. One part of the circuitry that failed was the serial interface. The failure analysis team decided to look at the serial interface failure mode first because of the simplicity of the test. After thorough analysis the FA team discovered increasing the data setup time at the serial port input allowed the device to work properly. SEM and FIB techniques were performed which identified a high impedance connection between a metal layer and the underlying via layer. The circuit was modified using a FIB edit, after which all vectors were read back correctly, without the additional set-up time.