10.2 A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface

2016 IEEE International Solid-State Circuits Conference (ISSCC) ◽

10.1109/isscc.2016.7417968 ◽

2016 ◽

Author(s):

Wei-Han Cho ◽

Yilei Li ◽

Yuan Du ◽

Chien-Heng Wong ◽

Jieqiong Du ◽

...

Keyword(s):

Memory Interface

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Differential DIMM OpenCAPI Memory Interface High Speed Channel Robustness and Scalability Study

2021 IEEE 71st Electronic Components and Technology Conference (ECTC) ◽

10.1109/ectc32696.2021.00207 ◽

2021 ◽

Author(s):

Biao Cai ◽

Kevin Mcilvain ◽

Junyan Tang ◽

Kyle Giesen ◽

Zhaoqing Chen ◽

...

Keyword(s):

Memory Interface

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An all-digital delay-locked loop for high-speed memory interface applications

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test ◽

10.1109/vlsi-dat.2014.6834900 ◽

2014 ◽

Author(s):

Shih-Lun Chen ◽

Ming-Jing Ho ◽

Yu-Ming Sun ◽

Maung Wai Lin ◽

Jung-Chin Lai

Keyword(s):

Delay Locked Loop ◽

Memory Interface

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Rambus: friend or foe? [high-speed memory interface technology manufacture]

IEEE Spectrum ◽

10.1109/6.920030 ◽

2001 ◽

Vol 38 (5) ◽

pp. 42-47 ◽

Author(s):

J. Kumagai

Keyword(s):

Memory Interface

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OpenCAPI Memory Interface Signal Integrity Study for High-Speed DDR5 Differential DIMM Channel with Standard Loss FR-4 Material and SNIA SFF-TA-1002 Connector

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) ◽

10.1109/ectc.2019.00186 ◽

2019 ◽

Author(s):

Biao Cai ◽

Jose Hejase ◽

Kyle Giesen ◽

Junyan Tang ◽

Brian Connolly ◽

...

Keyword(s):

Signal Integrity ◽

Memory Interface

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Machine Learning-Based Verilog-A Modeling for Supply Induced Jitter Sensitivity of High-Speed Memory Interface: Two Layer PCB Case Study

10.1109/emc/si/pi/emceurope52599.2021.9559310 ◽

2021 ◽

Author(s):

Michael Chang

Keyword(s):

Machine Learning ◽

Memory Interface

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A High-Speed Memory Interface Architecture for MPEG2 Video Decoder

2005 Conference on High Density Microsystem Design and Packaging and Component Failure Analysis ◽

10.1109/hdp.2005.251457 ◽

2005 ◽

Author(s):

Jia Xiaoling ◽

Chen Guanghua ◽

Zou Weiyu

Keyword(s):

Video Decoder ◽

Memory Interface ◽

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Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface

2018 International SoC Design Conference (ISOCC) ◽

10.1109/isocc.2018.8649918 ◽

2018 ◽

Author(s):

Kwanyeob Chae ◽

Billy Koo ◽

Jihun Oh ◽

Sanghune Park ◽

Jongshin Shin ◽

...

Keyword(s):

Low Power ◽

Design Methodologies ◽

Memory Interface

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High speed DDR memory interface design

2009 IEEE 8th International Conference on ASIC ◽

10.1109/asicon.2009.5351295 ◽

2009 ◽

Author(s):

Brian Zhao

Keyword(s):

Interface Design ◽

Memory Interface

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High-speed links for memory interface

2010 IEEE International Conference on Integrated Circuit Design and Technology ◽

10.1109/icicdt.2010.5510752 ◽

2010 ◽

Author(s):

Jae-Yoon Sim ◽

Seon-Kyoo Lee ◽

Young-Sik Kim ◽

Young-Soo Sohn ◽

Joo Sun Choi

Keyword(s):

Memory Interface

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Flexible and Resource Efficient FPGA-Based Quad Data Rate Memory Interface Design for High-Speed Data Acquisition Systems

2018 21st Euromicro Conference on Digital System Design (DSD) ◽

10.1109/dsd.2018.00038 ◽

2018 ◽

Author(s):

Nizam Ayyildiz

Keyword(s):

Data Acquisition ◽

Interface Design ◽

Data Rate ◽

Data Acquisition Systems ◽

High Speed Data Acquisition ◽

High Speed Data ◽

Memory Interface

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