An all-digital delay-locked loop for high-speed memory interface applications

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test ◽

10.1109/vlsi-dat.2014.6834900 ◽

2014 ◽

Author(s):

Shih-Lun Chen ◽

Ming-Jing Ho ◽

Yu-Ming Sun ◽

Maung Wai Lin ◽

Jung-Chin Lai

Keyword(s):

Delay Locked Loop ◽

Memory Interface

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Differential DIMM OpenCAPI Memory Interface High Speed Channel Robustness and Scalability Study

2021 IEEE 71st Electronic Components and Technology Conference (ECTC) ◽

10.1109/ectc32696.2021.00207 ◽

2021 ◽

Author(s):

Biao Cai ◽

Kevin Mcilvain ◽

Junyan Tang ◽

Kyle Giesen ◽

Zhaoqing Chen ◽

...

Keyword(s):

Memory Interface

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10.2 A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface

2016 IEEE International Solid-State Circuits Conference (ISSCC) ◽

10.1109/isscc.2016.7417968 ◽

2016 ◽

Author(s):

Wei-Han Cho ◽

Yilei Li ◽

Yuan Du ◽

Chien-Heng Wong ◽

Jieqiong Du ◽

...

Keyword(s):

Memory Interface

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Rambus: friend or foe? [high-speed memory interface technology manufacture]

IEEE Spectrum ◽

10.1109/6.920030 ◽

2001 ◽

Vol 38 (5) ◽

pp. 42-47 ◽

Author(s):

J. Kumagai

Keyword(s):

Memory Interface

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Algorithm, architecture, and implementation of algorithmic delay-locked loop based data recovery circuit for high-speed serial data communication

Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558) ◽

10.1109/asic.2001.954677 ◽

2002 ◽

Author(s):

Hongjiang Song

Keyword(s):

Data Communication ◽

Data Recovery ◽

Delay Locked Loop ◽

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OpenCAPI Memory Interface Signal Integrity Study for High-Speed DDR5 Differential DIMM Channel with Standard Loss FR-4 Material and SNIA SFF-TA-1002 Connector

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) ◽

10.1109/ectc.2019.00186 ◽

2019 ◽

Author(s):

Biao Cai ◽

Jose Hejase ◽

Kyle Giesen ◽

Junyan Tang ◽

Brian Connolly ◽

...

Keyword(s):

Signal Integrity ◽

Memory Interface

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Machine Learning-Based Verilog-A Modeling for Supply Induced Jitter Sensitivity of High-Speed Memory Interface: Two Layer PCB Case Study

10.1109/emc/si/pi/emceurope52599.2021.9559310 ◽

2021 ◽

Author(s):

Michael Chang

Keyword(s):

Machine Learning ◽

Memory Interface

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A High-Speed Memory Interface Architecture for MPEG2 Video Decoder

2005 Conference on High Density Microsystem Design and Packaging and Component Failure Analysis ◽

10.1109/hdp.2005.251457 ◽

2005 ◽

Author(s):

Jia Xiaoling ◽

Chen Guanghua ◽

Zou Weiyu

Keyword(s):

Video Decoder ◽

Memory Interface ◽

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All-digital Multi-phase Delay Locked Loop For Internal Timing Generation In Embedded And/or High-speed DRAMs

Symposium on VLSI Circuits ◽

10.1109/vlsic.1997.623830 ◽

1997 ◽

Author(s):

Gotoh ◽

Wakayama ◽

Saito ◽

Ogaw ◽

Tamura ◽

...

Keyword(s):

Phase Delay ◽

Delay Locked Loop ◽

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Dual Phase Detector Based Delay Locked Loop for High Speed Applications

International Journal of Engineering ◽

10.5829/idosi.ije.2014.27.04a.02 ◽

2014 ◽

Vol 27 (4 (A)) ◽

Keyword(s):

Phase Detector ◽

Delay Locked Loop

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Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications

Sensors ◽

10.3390/s16101593 ◽

2016 ◽

Vol 16 (10) ◽

pp. 1593 ◽

Author(s):

Bilal Abdulrazzaq ◽

Omar Ibrahim ◽

Shoji Kawahito ◽

Roslina Sidek ◽

Suhaidi Shafie ◽

...

Keyword(s):

Low Power ◽

Delay Locked Loop ◽

Adjustable Range

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