A Systolic Array Algorithm Based on Band-Convolution Structure for an Efficient VLSI Implementation of the Odd-Time Generalized Discrete Hartley Transform

2019 ◽  
Author(s):  
Doru Florin Chiper
Keyword(s):  
Systolic Array ◽  
Vlsi Implementation ◽  
Discrete Hartley Transform ◽  
Hartley Transform ◽  
Convolution Structure

scholarly journals Algorithm for Computation of DCT and its Implementation using a Systolic Architecture

2020 ◽  
Vol 9 (4) ◽  
pp. 2162-2167
Keyword(s):  
Systolic Array ◽  
Cost Effective ◽  
The Other ◽  
Systolic Architecture ◽  
Discrete Hartley Transform ◽  
Processing Elements ◽  
Suggested Algorithm ◽  
Hartley Transform ◽  
Sine Transform ◽  
Regular Design

In this paper a new algorithm for computing N-point DCT, where N=4r, r>1 is presented. A new algorithm has been derived that can compute the 1D DCT and it is realized in systolic array that utilizes identical processing elements (PE’s). The proposed approach can be used to obtain other transform like Discrete Sine Transform (DST), Discrete Hartley Transform (DHT). The suggested algorithm requires reduced number of multiplications as compared to the other methods of computing DCT. This suggests structure meets the architectural challenge and it is simple, regular design and cost-effective for special-purpose system.

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