A 5 Gbps 0.13 $\mu$m CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed Links

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2010.2047439 ◽

2010 ◽

Vol 45 (8) ◽

pp. 1533-1541 ◽

Author(s):

Mahmoud Reza Ahmadi ◽

Amir Amirkhany ◽

Ramesh Harjani

Keyword(s):

Clock And Data Recovery ◽

Data Recovery ◽

Recovery Scheme

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A 5Gbps 0.13μm CMOS pilot-based clock and data recovery scheme for high-speed links

2009 IEEE Custom Integrated Circuits Conference ◽

10.1109/cicc.2009.5280900 ◽

2009 ◽

Author(s):

Mahmoud Reza Ahmadi ◽

Amir Amirkhany ◽

Ramesh Harjani

Keyword(s):

Clock And Data Recovery ◽

Data Recovery ◽

Recovery Scheme

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Design of high-speed burst mode clock and data recovery IC for passive optical network

10.1117/12.628728 ◽

2005 ◽

Author(s):

Minhui Yan ◽

Xiaobin Hong ◽

Wei-Ping Huang ◽

Jin Hong

Keyword(s):

Optical Network ◽

Clock And Data Recovery ◽

Data Recovery ◽

Passive Optical Network ◽

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A Novel Clock and Data Recovery Scheme Based on Sigma-Delta Quantization

2005 6th International Conference on ASIC ◽

10.1109/icasic.2005.1611354 ◽

2006 ◽

Author(s):

Yuyu Liu ◽

Ning Ge ◽

Huazhong Yang ◽

Hui Wang

Keyword(s):

Clock And Data Recovery ◽

Data Recovery ◽

Sigma Delta ◽

Recovery Scheme

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A wide range, low power clock and data recovery scheme for RFID tags

Analog Integrated Circuits and Signal Processing ◽

10.1007/s10470-011-9744-0 ◽

2011 ◽

Vol 71 (1) ◽

pp. 101-106 ◽

Author(s):

Hang Yu ◽

Yan Li ◽

Lai Jiang ◽

Zhen Ji

Keyword(s):

Low Power ◽

Clock And Data Recovery ◽

Data Recovery ◽

Rfid Tags ◽

Recovery Scheme

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A Robust High Speed Serial PHY Architecture With Feed-Forward Correction Clock and Data Recovery

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2009.2020230 ◽

2009 ◽

Vol 44 (7) ◽

pp. 1914-1926 ◽

Author(s):

William Redman-White ◽

Martin Bugbee ◽

Steve Dobbs ◽

Xinyan Wu ◽

Richard Balmford ◽

...

Keyword(s):

Clock And Data Recovery ◽

Data Recovery ◽

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Clock- and Data-Recovery Circuit With Independently Controlled Eye-Tracking Loop for High-Speed Graphic DRAMs

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2011.2158254 ◽

2011 ◽

Vol 58 (7) ◽

pp. 422-426 ◽

Author(s):

Jun-Yong Song ◽

Oh-Kyong Kwon

Keyword(s):

Eye Tracking ◽

Clock And Data Recovery ◽

Data Recovery ◽

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Challenges in the design high-speed clock and data recovery circuits

IEEE Communications Magazine ◽

10.1109/mcom.2002.1024421 ◽

2002 ◽

Vol 40 (8) ◽

pp. 94-101 ◽

Author(s):

B. Razavi

Keyword(s):

Clock And Data Recovery ◽

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Basics of Clock and Data Recovery Circuits: Exploring High-Speed Serial Links

IEEE Solid-State Circuits Magazine ◽

10.1109/mssc.2019.2939342 ◽

2020 ◽

Vol 12 (1) ◽

pp. 25-38

Author(s):

Amir Amirkhany

Keyword(s):

Clock And Data Recovery ◽

Data Recovery ◽

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A novel clock and data recovery scheme for 10Gbps source synchronous receiver in 65nm CMOS

2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) ◽

10.1109/mwscas.2012.6292174 ◽

2012 ◽

Author(s):

Ke Huang ◽

Ziqiang Wang ◽

Xuqiang Zheng ◽

Xuan Ma ◽

Kunzhi Yu ◽

...

Keyword(s):

Clock And Data Recovery ◽

Data Recovery ◽

Recovery Scheme

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Bit-Error Rate Estimation for Bang-Bang Clock and Data Recovery Circuit in High-Speed Serial Links

26th IEEE VLSI Test Symposium (vts 2008) ◽

10.1109/vts.2008.21 ◽

2008 ◽

Author(s):

Dongwoo Hong ◽

Kwang-Ting Cheng

Keyword(s):

Bit Error Rate ◽

Clock And Data Recovery ◽

Data Recovery ◽

Serial Links ◽

Rate Estimation

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