Clock- and Data-Recovery Circuit With Independently Controlled Eye-Tracking Loop for High-Speed Graphic DRAMs

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2011.2158254 ◽

2011 ◽

Vol 58 (7) ◽

pp. 422-426 ◽

Author(s):

Jun-Yong Song ◽

Oh-Kyong Kwon

Keyword(s):

Eye Tracking ◽

Clock And Data Recovery ◽

Data Recovery ◽

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Design of high-speed burst mode clock and data recovery IC for passive optical network

10.1117/12.628728 ◽

2005 ◽

Author(s):

Minhui Yan ◽

Xiaobin Hong ◽

Wei-Ping Huang ◽

Jin Hong

Keyword(s):

Optical Network ◽

Clock And Data Recovery ◽

Data Recovery ◽

Passive Optical Network ◽

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A Robust High Speed Serial PHY Architecture With Feed-Forward Correction Clock and Data Recovery

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2009.2020230 ◽

2009 ◽

Vol 44 (7) ◽

pp. 1914-1926 ◽

Author(s):

William Redman-White ◽

Martin Bugbee ◽

Steve Dobbs ◽

Xinyan Wu ◽

Richard Balmford ◽

...

Keyword(s):

Clock And Data Recovery ◽

Data Recovery ◽

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Challenges in the design high-speed clock and data recovery circuits

IEEE Communications Magazine ◽

10.1109/mcom.2002.1024421 ◽

2002 ◽

Vol 40 (8) ◽

pp. 94-101 ◽

Author(s):

B. Razavi

Keyword(s):

Clock And Data Recovery ◽

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Basics of Clock and Data Recovery Circuits: Exploring High-Speed Serial Links

IEEE Solid-State Circuits Magazine ◽

10.1109/mssc.2019.2939342 ◽

2020 ◽

Vol 12 (1) ◽

pp. 25-38

Author(s):

Amir Amirkhany

Keyword(s):

Clock And Data Recovery ◽

Data Recovery ◽

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A 5Gbps 0.13μm CMOS pilot-based clock and data recovery scheme for high-speed links

2009 IEEE Custom Integrated Circuits Conference ◽

10.1109/cicc.2009.5280900 ◽

2009 ◽

Author(s):

Mahmoud Reza Ahmadi ◽

Amir Amirkhany ◽

Ramesh Harjani

Keyword(s):

Clock And Data Recovery ◽

Data Recovery ◽

Recovery Scheme

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Bit-Error Rate Estimation for Bang-Bang Clock and Data Recovery Circuit in High-Speed Serial Links

26th IEEE VLSI Test Symposium (vts 2008) ◽

10.1109/vts.2008.21 ◽

2008 ◽

Author(s):

Dongwoo Hong ◽

Kwang-Ting Cheng

Keyword(s):

Bit Error Rate ◽

Clock And Data Recovery ◽

Data Recovery ◽

Serial Links ◽

Rate Estimation

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Event-Driven Model for High Speed End-to-End Simulations of Transmission System with Non-Linear Optical Elements and Cascaded Clock-and-Data Recovery Circuits

2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ◽

10.1109/vlsi-dat.2019.8742030 ◽

2019 ◽

Author(s):

Jun Matsui ◽

Hisakatsu Yamaguchi

Keyword(s):

Clock And Data Recovery ◽

Transmission System ◽

Data Recovery ◽

Optical Elements ◽

Event Driven ◽

Linear Optical ◽

Linear Optical Elements

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All-optical clock and data recovery using self-pulsating lasers for high-speed optical networks

5th International Conference on Energy Aware Computing Systems & Applications ◽

10.1109/iceac.2015.7352193 ◽

2015 ◽

Author(s):

Yasmine El-Sayed ◽

Amr Wageeh ◽

Tawfik Ismail ◽

Hassan Mostafa

Keyword(s):

Optical Networks ◽

Clock And Data Recovery ◽

Data Recovery ◽

Optical Clock ◽

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Design of high-speed clock and data recovery circuits

Analog Integrated Circuits and Signal Processing ◽

10.1007/s10470-007-9093-1 ◽

2007 ◽

Vol 52 (1-2) ◽

pp. 15-23 ◽

Author(s):

Tan Kok-Siang ◽

Mohd-Shahiman Sulaiman ◽

Chuah Hean-Teik ◽

Manoj Sachdev

Keyword(s):

Clock And Data Recovery ◽

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A 10 GB/S EQUALIZER WITH INTEGRATED CLOCK AND DATA RECOVERY FOR OPTICAL COMMUNICATION SYSTEMS

International Journal of High Speed Electronics and Systems ◽

10.1142/s0129156405003314 ◽

2005 ◽

Vol 15 (03) ◽

pp. 525-548 ◽

Author(s):

D. S. MCPHERSON ◽

H. TRAN ◽

P. POPESCU

Keyword(s):

Communication Systems ◽

Automatic Gain Control ◽

Polarization Mode Dispersion ◽

Gain Control ◽

Clock And Data Recovery ◽

Data Recovery ◽

Decision Feedback ◽

Bicmos Technology ◽

Feedforward Equalizer

A 10 Gb/s analog continuous-time equalizer with integrated clock and data recovery circuit is presented. It is designed to recover signals degraded by chromatic and polarization mode dispersion. The key components in the design are a feedforward equalizer and a decision feedback equalizer, the parameters of which are electronically adjustable. Both circuit blocks are fully described and characterized with emphasis on minimizing self-induced distortion and maximizing high-speed performance. In addition to the equalizer and the clock and data recovery, the circuit also includes an integrated automatic gain control. The circuit is implemented in a commercial 0.18 μm SiGe BiCMOS technology and consumes 900 mW. The capacity of the equalizer to mitigate signal impairments is demonstrated using three electrically generated channels.

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