A 3.5–6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH $\Delta \Sigma $ -TDC for Low In-Band Phase Noise

2017 ◽  
Vol 52 (7) ◽  
pp. 1885-1903 ◽  
Author(s):  
Ying Wu ◽  
Mina Shahmohammadi ◽  
Yue Chen ◽  
Ping Lu ◽  
Robert Bogdan Staszewski
Author(s):  
Muhammed Bolatkale ◽  
Lucien J. Breems ◽  
Kofi A. A. Makinwa

2007 ◽  
Vol 42 (12) ◽  
pp. 2639-2650 ◽  
Author(s):  
Ashok Swaminathan ◽  
Kevin J. Wang ◽  
Ian Galton

2015 ◽  
Vol 643 ◽  
pp. 149-155 ◽  
Author(s):  
Yusuke Osawa ◽  
Daiki Hirabayashi ◽  
Naohiro Harigai ◽  
Haruo Kobayashi ◽  
Osamu Kobayashi ◽  
...  

This paper describes a phase noise measurement and testing technique for a clock using a delta-sigma time-to-digital converter (TDC) and verifies its effectiveness with MATLAB simulations. The proposed technique can be implemented with relatively small circuitry, based on the following: (i) The clock under test (CUT) is a repetitive signal. (ii) The time resolution with CUT and a reference clock can be finer with longer measurement time with the delta-sigma TDC. (iii) The phase noise power spectrum can be calculated from the delta-sigma TDC output data using FFT. High performance spectrum analyzers with long measurement time (several ten seconds order due to average of several-time phase measurement results), which are very costly in mass production testing, are not be needed for phase noise measurement with the proposed technique. Our simulation used the input clock of 1 MHz in several phase fluctuation cases, and we observed that the phase fluctuation spectrum at the expected frequency from TDC output power spectrum obtained by FFT. We also investigated the amount of phase fluctuation with our theoretical calculation, which agrees with the simulation results.


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