A 2.4 GHz Quadrature-Input Programmable Fractional Frequency Divider

2011 ◽  
Vol 21 (1) ◽  
pp. 34-36 ◽  
Author(s):  
Ka Fai Chang ◽  
Kwok-Keung M. Cheng
Keyword(s):  
Frequency Divider ◽  
Fractional Frequency

A quad-band W-CDMA transceiver IC-direct conversion architecture with fractional frequency divider

2012 ◽  
Vol 8 (1) ◽  
pp. 49-55
Author(s):  
Hiroshi Kamizuma ◽  
Yukinori Akamine ◽  
Taizo Yamawaki ◽  
Kazuhiko Hikasa
Keyword(s):  
Direct Conversion ◽  
Frequency Divider ◽  
Fractional Frequency

Design and Implementation of a Fractional Frequency Divider for Dual Mode Wireless Receivers

2012 ◽  
Vol 229-231 ◽  
pp. 1591-1594
Author(s):  
Xiang Ning Fan ◽  
Bin Li ◽  
Wei Wei Zhu ◽  
Lu Yu ◽  
Yu Jie Wang
Keyword(s):  
Frequency Synthesizer ◽  
Fractional Part ◽  
Frequency Divider ◽  
Wireless Receivers ◽  
Cmos Process ◽  
Dual Mode ◽  
Chip Area ◽  
Fractional Frequency ◽  
Delta Sigma ◽  
Operating Frequency Range

In this paper, a fractional frequency divider (FFD) is designed for Phase-Locked-Loop (PLL) based Frequency Synthesizer, which can be used for GPS/Galileo and WCDMA dual-mode receivers. Based on a dual-modulus prescaler (DMP) and a programmable frequency divider (FD), the integer part can cover from 513 to 760. The fractional part is realized by improved MASH1-1-1 Delta-Sigma (Δ-Σ) modulator (DSM). The whole fractional frequency divider is implemented in TSMC 0.18μm CMOS process, occupying a chip area of 0.714mm2. With the voltage supply of 1.8V, the operating frequency range of the fractional frequency divider is 0.5-5.3GHz; and its supply current is about 5.9mA.

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